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Message-ID: <20180116200149.zffwdbjwj53ba7oj@pd.tnic>
Date:   Tue, 16 Jan 2018 21:01:49 +0100
From:   Borislav Petkov <bp@...en8.de>
To:     "Luck, Tony" <tony.luck@...el.com>
Cc:     Jia Zhang <zhang.jia@...ux.alibaba.com>,
        "hmh@....eng.br" <hmh@....eng.br>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] x86/microcode/intel: Extend BDW late-loading with LLC
 size check

On Tue, Jan 16, 2018 at 05:24:27PM +0000, Luck, Tony wrote:
> > I'll look for someone who can confirm the 2.5MB/core detail.
> 
> Ok ... re-read the erratum.  The 2.5MB/core is clear.  The E5+E7 is clear.
> 
> No mention of the platform ID, but Jia is dropping that part.
> 
> Boris ... what specific questions remain?

This magic:

	llc_size_per_core(c) > 2621440

as a reliable detection characteristic whether the patch is good to
apply late. There must be a more reliable way to detect that.

Also, the testing order is:

           llc_size_per_core(c) > 2621440 &&
            c->microcode < 0x0b000021) {

so if the LLC size per core check fails, the microcode revision being <
0x0b000021 doesn't matter. I.e., on machines with LLC-per-core < 2.5M,
we can update even with revisions < 0x0b000021.

Is that ordering correct?

Also, this heuristic is not documented in the public doc AFAICT - I'm
guessing that'll change soon...?

Thx.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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