linux-kernel - [tip:x86/pti] x86/msr: Add definitions for new speculation control MSRs

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Date:   Fri, 26 Jan 2018 07:00:58 -0800
From:   tip-bot for David Woodhouse <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     dwmw@...zon.co.uk, linux-kernel@...r.kernel.org,
        gregkh@...uxfoundation.org, hpa@...or.com, mingo@...nel.org,
        tglx@...utronix.de
Subject: [tip:x86/pti] x86/msr: Add definitions for new speculation control
 MSRs

Commit-ID:  1e340c60d0dd3ae07b5bedc16a0469c14b9f3410
Gitweb:     https://git.kernel.org/tip/1e340c60d0dd3ae07b5bedc16a0469c14b9f3410
Author:     David Woodhouse <dwmw@...zon.co.uk>
AuthorDate: Thu, 25 Jan 2018 16:14:12 +0000
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Fri, 26 Jan 2018 15:53:17 +0100

x86/msr: Add definitions for new speculation control MSRs

Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and ARCH_CAPABILITIES.

See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf

Signed-off-by: David Woodhouse <dwmw@...zon.co.uk>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: gnomes@...rguk.ukuu.org.uk
Cc: ak@...ux.intel.com
Cc: ashok.raj@...el.com
Cc: dave.hansen@...el.com
Cc: karahmed@...zon.de
Cc: arjan@...ux.intel.com
Cc: torvalds@...ux-foundation.org
Cc: peterz@...radead.org
Cc: bp@...en8.de
Cc: pbonzini@...hat.com
Cc: tim.c.chen@...ux.intel.com
Cc: gregkh@...ux-foundation.org
Link: https://lkml.kernel.org/r/1516896855-7642-5-git-send-email-dwmw@amazon.co.uk

---
 arch/x86/include/asm/msr-index.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index fa11fb1..eb83ff1 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -39,6 +39,13 @@
 
 /* Intel MSRs. Some also available on other CPUs */
 
+#define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */
+#define SPEC_CTRL_IBRS			(1 << 0)   /* Indirect Branch Restricted Speculation */
+#define SPEC_CTRL_STIBP			(1 << 1)   /* Single Thread Indirect Branch Predictors */
+
+#define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */
+#define PRED_CMD_IBPB			(1 << 0)   /* Indirect Branch Prediction Barrier */
+
 #define MSR_PPIN_CTL			0x0000004e
 #define MSR_PPIN			0x0000004f
 
@@ -57,6 +64,11 @@
 #define SNB_C3_AUTO_UNDEMOTE		(1UL << 28)
 
 #define MSR_MTRRcap			0x000000fe
+
+#define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
+#define ARCH_CAP_RDCL_NO		(1 << 0)   /* Not susceptible to Meltdown */
+#define ARCH_CAP_IBRS_ALL		(1 << 1)   /* Enhanced IBRS support */
+
 #define MSR_IA32_BBL_CR_CTL		0x00000119
 #define MSR_IA32_BBL_CR_CTL3		0x0000011e