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Message-Id: <20180206044905.30508-4-icenowy@aosc.io>
Date: Tue, 6 Feb 2018 12:48:58 +0800
From: Icenowy Zheng <icenowy@...c.io>
To: Liam Girdwood <lgirdwood@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Maxime Ripard <maxime.ripard@...tlin.com>,
Chen-Yu Tsai <wens@...e.org>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...glegroups.com,
Ondrej Jirman <megous@...ous.com>,
Icenowy Zheng <icenowy@...c.io>
Subject: [PATCH v2 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node
From: Ondrej Jirman <megous@...ous.com>
H3/H5 SoCs contain an I2C controller optionally available
on the PL0 and PL1 pins. This patch adds pinmux configuration
for this controller.
Signed-off-by: Ondrej Jirman <megous@...ous.com>
[Icenowy: change commit message, node name and function name]
Signed-off-by: Icenowy Zheng <icenowy@...c.io>
Reviewed-by: Chen-Yu Tsai <wens@...e.org>
---
Changes in v2:
- Added Chen-Yu's Review tag.
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 7a83b15225c7..fc602aed60a6 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -731,6 +731,11 @@
pins = "PL11";
function = "s_cir_rx";
};
+
+ r_i2c_pins: r-i2c {
+ pins = "PL0", "PL1";
+ function = "s_i2c";
+ };
};
};
};
--
2.15.1
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