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Message-Id: <20180206044905.30508-5-icenowy@aosc.io>
Date: Tue, 6 Feb 2018 12:48:59 +0800
From: Icenowy Zheng <icenowy@...c.io>
To: Liam Girdwood <lgirdwood@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Maxime Ripard <maxime.ripard@...tlin.com>,
Chen-Yu Tsai <wens@...e.org>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...glegroups.com,
Ondrej Jirman <megous@...ous.com>,
Icenowy Zheng <icenowy@...c.io>
Subject: [PATCH v2 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller
From: Ondrej Jirman <megous@...ous.com>
Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank.
Add support for it in the device tree.
Signed-off-by: Ondrej Jirman <megous@...ous.com>
[Icenowy: Change to use r_ccu and change pinmux node name]
Signed-off-by: Icenowy Zheng <icenowy@...c.io>
Reviewed-by: Chen-Yu Tsai <wens@...e.org>
---
Changes in v2:
- Added Chen-Yu's Review tag.
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index fc602aed60a6..57606900a949 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -716,6 +716,19 @@
status = "disabled";
};
+ r_i2c: i2c@...2400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01f02400 0x400>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pins>;
+ clocks = <&r_ccu CLK_APB0_I2C>;
+ resets = <&r_ccu RST_APB0_I2C>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
r_pio: pinctrl@...2c00 {
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.15.1
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