linux-kernel - Re: [PATCH] arm64: Add missing Falkor part number for branch predictor hardening

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Message-ID: <86po5ah9fj.wl-marc.zyngier@arm.com>
Date:   Mon, 12 Feb 2018 08:57:36 +0000
From:   Marc Zyngier <marc.zyngier@....com>
To:     Shanker Donthineni <shankerd@...eaurora.org>
Cc:     Will Deacon <will.deacon@....com>,
        Christoffer Dall <christoffer.dall@...aro.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        kvmarm <kvmarm@...ts.cs.columbia.edu>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Catalin Marinas <catalin.marinas@....com>,
        Vikram Sethi <vikrams@...eaurora.org>,
        Sean Campbell <scampbel@...eaurora.org>,
        Thomas Speier <tspeier@...eaurora.org>
Subject: Re: [PATCH] arm64: Add missing Falkor part number for branch predictor hardening

On Mon, 12 Feb 2018 01:16:15 +0000,
Shanker Donthineni wrote:
> 
> References to CPU part number MIDR_QCOM_FALKOR were dropped from the
> mailing list patch due to mainline/arm64 branch dependency. So this
> patch adds the missing part number.
> 
> Fixes: ec82b567a74f ("arm64: Implement branch predictor hardening for Falkor")
> Signed-off-by: Shanker Donthineni <shankerd@...eaurora.org>
> ---
>  arch/arm64/kernel/cpu_errata.c | 9 +++++++++
>  arch/arm64/kvm/hyp/switch.c    | 4 +++-
>  2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 0782359..52f15cd 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -408,6 +408,15 @@ static int qcom_enable_link_stack_sanitization(void *data)
>  	},
>  	{
>  		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
> +		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
> +		.enable = qcom_enable_link_stack_sanitization,
> +	},
> +	{
> +		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
> +		MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
> +	},
> +	{
> +		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
>  		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
>  		.enable = enable_smccc_arch_workaround_1,
>  	},
> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> index 116252a8..870f4b1 100644
> --- a/arch/arm64/kvm/hyp/switch.c
> +++ b/arch/arm64/kvm/hyp/switch.c
> @@ -407,8 +407,10 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
>  		u32 midr = read_cpuid_id();
>  
>  		/* Apply BTAC predictors mitigation to all Falkor chips */
> -		if ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)
> +		if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
> +		    ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) {
>  			__qcom_hyp_sanitize_btac_predictors();
> +		}
>  	}
>  
>  	fp_enabled = __fpsimd_enabled();

Acked-by: Marc Zyngier <marc.zyngier@....com>

I'd suggest this goes via the arm64 tree as a matter of consistency
with the rest of the variant-2 series.

Thanks,

	M.

-- 
Jazz is not dead, it just smell funny.