[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20180214163838.GB3986@saruman>
Date: Wed, 14 Feb 2018 16:38:39 +0000
From: James Hogan <jhogan@...nel.org>
To: Alexandre Belloni <alexandre.belloni@...e-electrons.com>
Cc: Ralf Baechle <ralf@...ux-mips.org>, linux-mips@...ux-mips.org,
linux-kernel@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
devicetree@...r.kernel.org
Subject: Re: [PATCH v3 1/8] dt-bindings: mips: Add bindings for Microsemi SoCs
On Tue, Jan 16, 2018 at 11:12:33AM +0100, Alexandre Belloni wrote:
> +o CPU system control:
> +
> +The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
> +the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
> +endianess, CPU bus control, CPU status.
nit: checkpatch suggests endianess should be spelt endianness
Cheers
James
Download attachment "signature.asc" of type "application/pgp-signature" (834 bytes)
Powered by blists - more mailing lists