lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sat, 17 Feb 2018 01:10:27 +0100
From:   Heiko Stuebner <heiko@...ech.de>
To:     Enric Balletbo i Serra <enric.balletbo@...labora.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Brian Norris <briannorris@...omium.org>, dianders@...omium.org,
        Chris Zhong <zyw@...k-chips.com>,
        William wu <wulf@...k-chips.com>, hl@...k-chips.com,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kernel@...labora.com
Subject: Re: [PATCH v3 5/6] phy: rockchip-typec: support DP phy switch

Am Freitag, 16. Februar 2018, 13:09:55 CET schrieb Enric Balletbo i Serra:
> From: Chris Zhong <zyw@...k-chips.com>
> 
> There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence
> only one PHY can connect to DP controller at one time, the other should
> be disconnected. The GRF_SOC_CON26 register has a switch bit to do it,
> set this bit means enable PHY 1, clear this bit means enable PHY 0.
> 
> Signed-off-by: Chris Zhong <zyw@...k-chips.com>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
> ---

Reviewed-by: Heiko Stuebner <heiko@...ech.de>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ