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Message-ID: <4816286.2JUx8CKC3E@phil>
Date:   Sat, 17 Feb 2018 01:09:52 +0100
From:   Heiko Stuebner <heiko@...ech.de>
To:     Enric Balletbo i Serra <enric.balletbo@...labora.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Brian Norris <briannorris@...omium.org>, dianders@...omium.org,
        Chris Zhong <zyw@...k-chips.com>,
        William wu <wulf@...k-chips.com>, hl@...k-chips.com,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kernel@...labora.com
Subject: Re: [PATCH v3 4/6] phy: rockchip-typec: force to USB2 if DP at 4 lanes mode

Am Freitag, 16. Februar 2018, 13:09:54 CET schrieb Enric Balletbo i Serra:
> From: Chris Zhong <zyw@...k-chips.com>
> 
> The usb3tousb2_en BIT will be clear to 0 in probe(), it make USB
> controller work at USB3 mode, and if the USB phy is turned on with DP
> only mode(4 lanes DP), the rockchip_usb3_phy_power_on() will return
> directly, so usb3_host_disable and usb3_host_port these 2 BIT will keep
> a same value as coreboot. In coreboot, these 3 BITs are set as USB2
> mode, but now one of the bits is changed to USB3, it make USB controller
> work at a unknown status.
> 
> These 3 BITs should be changed to USB2, if the Type-C works at 4 lanes
> mode, and then switch it back to USB3 mode, when USB disconnect.
> 
> Signed-off-by: Chris Zhong <zyw@...k-chips.com>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>

Reviewed-by: Heiko Stuebner <heiko@...ech.de>

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