linux-kernel - Re: [PATCH] arm64: Make L1_CACHE

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Message-ID: <9a5190d1-eb8d-0275-d8d9-39de622a679c@jonmasters.org>
Date:   Mon, 19 Feb 2018 18:46:14 -0500
From:   Jon Masters <jcm@...masters.org>
To:     Florian Fainelli <f.fainelli@...il.com>,
        Timur Tabi <timur@...eaurora.org>,
        linux-arm-kernel@...ts.infradead.org
Cc:     tchalamarla@...ium.com, rrichter@...ium.com, opendmb@...il.com,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        Mark Rutland <mark.rutland@....com>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] arm64: Make L1_CACHE_SHIFT configurable

On 02/12/2018 07:17 PM, Florian Fainelli wrote:
> On 02/12/2018 04:10 PM, Timur Tabi wrote:
>> On 02/12/2018 05:57 PM, Florian Fainelli wrote:
>>> That is debatable, is there a good publicly available table of what the
>>> typical L1 cache line size is on ARMv8 platforms?

With a server hat on...

There are many ARMv8 server platforms that do 64b today, but future
designs are likely to head toward 128b (for a variety of reasons). Many
of the earlier designs were 64b because that's what certain other arches
were using in their server cores. I doubt Vulcan will remain a unique
and special case for very long. On the CCIX side of things, I've been
trying to push people to go with 128b lines in future designs too.

Jon.