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Message-ID: <20180306210338.GD12128@flask>
Date: Tue, 6 Mar 2018 22:03:38 +0100
From: Radim Krcmar <rkrcmar@...hat.com>
To: Janakarajan Natarajan <Janakarajan.Natarajan@....com>
Cc: kvm@...r.kernel.org, x86@...nel.org, linux-kernel@...r.kernel.org,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H . Peter Anvin" <hpa@...or.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Len Brown <len.brown@...el.com>, Borislav Petkov <bp@...e.de>,
Kyle Huey <me@...ehuey.com>,
Tom Lendacky <thomas.lendacky@....com>
Subject: Re: [PATCH v5 1/3] x86/msr: Add AMD Core Perf Extension MSRs
2018-02-05 13:24-0600, Janakarajan Natarajan:
> Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
>
> Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@....com>
> ---
> arch/x86/include/asm/msr-index.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index e7b983a..2885363 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -341,7 +341,21 @@
>
> /* Fam 15h MSRs */
> #define MSR_F15H_PERF_CTL 0xc0010200
> +#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
> +#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
> +#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)
> +#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)
> +#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)
> +#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
> +
> #define MSR_F15H_PERF_CTR 0xc0010201
> +#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR
> +#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)
> +#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)
> +#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)
> +#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)
> +#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)
> +
x86 maintainers,
are you ok with this going through the kvm tree?
Thanks.
> #define MSR_F15H_NB_PERF_CTL 0xc0010240
> #define MSR_F15H_NB_PERF_CTR 0xc0010241
> #define MSR_F15H_PTSC 0xc0010280
> --
> 2.7.4
>
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