linux-kernel - [tip:x86/mm] x86/cpufeatures: Add Intel PCONFIG cpufeature

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Message-ID: <tip-7958b2246fadf54b7ff820a2a5a2c5ca1554716f@git.kernel.org>
Date:   Mon, 12 Mar 2018 05:21:23 -0700
From:   "tip-bot for Kirill A. Shutemov" <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     dave.hansen@...el.com, linux-kernel@...r.kernel.org,
        peterz@...radead.org, torvalds@...ux-foundation.org,
        kai.huang@...ux.intel.com, kirill.shutemov@...ux.intel.com,
        hpa@...or.com, tglx@...utronix.de, mingo@...nel.org,
        thomas.lendacky@....com
Subject: [tip:x86/mm] x86/cpufeatures: Add Intel PCONFIG cpufeature

Commit-ID:  7958b2246fadf54b7ff820a2a5a2c5ca1554716f
Gitweb:     https://git.kernel.org/tip/7958b2246fadf54b7ff820a2a5a2c5ca1554716f
Author:     Kirill A. Shutemov <kirill.shutemov@...ux.intel.com>
AuthorDate: Mon, 5 Mar 2018 19:25:51 +0300
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Mon, 12 Mar 2018 12:09:53 +0100

x86/cpufeatures: Add Intel PCONFIG cpufeature

CPUID.0x7.0x0:EDX[18] indicates whether Intel CPU support PCONFIG instruction.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@...ux.intel.com>
Cc: Dave Hansen <dave.hansen@...el.com>
Cc: Kai Huang <kai.huang@...ux.intel.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Tom Lendacky <thomas.lendacky@....com>
Cc: linux-mm@...ck.org
Link: http://lkml.kernel.org/r/20180305162610.37510-4-kirill.shutemov@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 16898eb813f5..d554c11e01ff 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -329,6 +329,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
 #define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */
 #define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
+#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
 #define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */