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Message-ID: <CAHp75Vdvmbhj9kb+D7qSbBQFD52n=rHWukvAJgGXxCbcnNSCyg@mail.gmail.com>
Date: Tue, 13 Mar 2018 19:31:39 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: "Liang, Kan" <kan.liang@...ux.intel.com>
Cc: "Kroening, Gary" <gary.kroening@....com>,
"mingo@...hat.com" <mingo@...hat.com>,
"hpa@...or.com" <hpa@...or.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"peterz@...radead.org" <peterz@...radead.org>,
"Travis, Mike" <mike.travis@....com>,
"Banman, Andrew" <abanman@....com>,
"Sivanich, Dimitri" <dimitri.sivanich@....com>,
"Anderson, Russ" <russ.anderson@....com>,
"x86@...nel.org" <x86@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on
multi-pci-segment arches
On Tue, Mar 13, 2018 at 7:28 PM, Liang, Kan <kan.liang@...ux.intel.com> wrote:
>>>>>> +#define SKX_CAPID6 0x9c
^^^ This needs a comment.
>>> It looks it doesn't use capability.
> $ lspci -nk -vvv -xx -s 16:1e.3
> 16:1e.3 0880: 8086:2083 (rev 04)
> Subsystem: 8086:0000
> Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B- DisINTx-
> Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
> 00: 86 80 83 20 00 00 00 00 04 00 80 08 00 00 80 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Pity.
--
With Best Regards,
Andy Shevchenko
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