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Date:   Wed, 14 Mar 2018 00:38:40 +0100
From:   Heiko Stuebner <>
To:     Derek Basehore <>
Subject: Re: [PATCH] clk: rockchip: Add 1.6GHz PLL rate

Am Dienstag, 13. März 2018, 21:37:19 CET schrieb Derek Basehore:
> We need this rate to generate 100, 200, and 228.57MHz from the same
> PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
> and external display.
> Signed-off-by: Derek Basehore <>

applied for 4.17


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