linux-kernel - Re: [PATCH RFC rebase 3/9] powerpc/64: Use barrier

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Message-ID: <CA+55aFxYOrn0XRPF8EXvizqAf3GOGmUxu-aKrqvtOsbgxwP2tg@mail.gmail.com>
Date:   Fri, 16 Mar 2018 10:08:37 -0700
From:   Linus Torvalds <torvalds@...ux-foundation.org>
To:     Michal Suchánek <msuchanek@...e.de>
Cc:     Nicholas Piggin <npiggin@...il.com>,
        Kate Stewart <kstewart@...uxfoundation.org>,
        Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>,
        Mahesh Salgaonkar <mahesh@...ux.vnet.ibm.com>,
        Al Viro <viro@...iv.linux.org.uk>,
        Paul Mackerras <paulus@...ba.org>,
        Michael Neuling <mikey@...ling.org>,
        "Bryant G. Ly" <bryantly@...ux.vnet.ibm.com>,
        "Naveen N. Rao" <naveen.n.rao@...ux.vnet.ibm.com>,
        Daniel Axtens <dja@...ens.net>,
        Cédric Le Goater <clg@...d.org>,
        David Gibson <david@...son.dropbear.id.au>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Sergey Senozhatsky <sergey.senozhatsky@...il.com>,
        Masami Hiramatsu <mhiramat@...nel.org>,
        Andrew Donnellan <andrew.donnellan@....ibm.com>,
        Philippe Ombredanne <pombredanne@...b.com>,
        Joe Perches <joe@...ches.com>,
        "Oliver O'Halloran" <oohall@...il.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        ppc-dev <linuxppc-dev@...ts.ozlabs.org>,
        "Tobin C. Harding" <me@...in.cc>
Subject: Re: [PATCH RFC rebase 3/9] powerpc/64: Use barrier_nospec in syscall entry

On Fri, Mar 16, 2018 at 2:15 AM, Michal Suchánek <msuchanek@...e.de> wrote:
>
> As far as I understand barriers they separate code before the barrier
> and code after the barrier.

Almost certainly not. Even if you were to do an expensive
serialization before the branch, the branch will still predict after
the serialization.

The thing is, it doesn't make sense to insert a barrier before a
conditional branch for Spectre mitigation.

The problem is not that the data isn't ready for the branch - the
problem is that the branch is predicted _regardless_ of the data.

Sure, some micro-architecture might not predict branches at all if
they have a stable conditional, so a barrier _can_ make sense.

But fundamentally, good branch prediction - in order to be optimal -
has to happen before instructions have even been parsed, much less
things like "stable conditional register state" having been decided
on. You'll want to do I$ prefetching etc.

So the problem is that even if the data is ready, the branch will be
predicted according to some unrelated historical data, and a barrier
to make the branch conditional be stable is pointless.

A barrier *after* the branch, making sure that you don't actually
start executing instructions past it (even if you might have predicted
and fetched stuff past it) *if* you have mis-predicted the previous
branch, is what a sane architecture would specify.

Of course, on x86, we mostly tried to avoid branch prediction being
the critical problem and having to have barriers by just making it an
address generation dependency instead. That should presumably work on
powerpc too, since address generation is part of the memory ordering
definition. But obviously a microarchitecture *could* end up
speculating and just redoing even for memory ordering, and maybe the
ppc architects prefer the barrier since they are already used to crazy
and not very well architected barriers elsewhere.

              Linus