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Message-ID: <873710i1yt.fsf@concordia.ellerman.id.au>
Date: Sat, 17 Mar 2018 00:28:42 +1100
From: Michael Ellerman <mpe@...erman.id.au>
To: Michal Suchánek <msuchanek@...e.de>,
Nicholas Piggin <npiggin@...il.com>
Cc: Kate Stewart <kstewart@...uxfoundation.org>,
Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>,
Mahesh Salgaonkar <mahesh@...ux.vnet.ibm.com>,
Al Viro <viro@...iv.linux.org.uk>,
Paul Mackerras <paulus@...ba.org>,
Michael Neuling <mikey@...ling.org>,
"Bryant G. Ly" <bryantly@...ux.vnet.ibm.com>,
"Naveen N. Rao" <naveen.n.rao@...ux.vnet.ibm.com>,
Daniel Axtens <dja@...ens.net>,
Cédric Le Goater <clg@...d.org>,
David Gibson <david@...son.dropbear.id.au>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-kernel@...r.kernel.org,
Sergey Senozhatsky <sergey.senozhatsky@...il.com>,
Masami Hiramatsu <mhiramat@...nel.org>,
Andrew Donnellan <andrew.donnellan@....ibm.com>,
Philippe Ombredanne <pombredanne@...b.com>,
Joe Perches <joe@...ches.com>,
Oliver O'Halloran <oohall@...il.com>,
Andrew Morton <akpm@...ux-foundation.org>,
linuxppc-dev@...ts.ozlabs.org, "Tobin C. Harding" <me@...in.cc>
Subject: Re: [PATCH RFC rebase 3/9] powerpc/64: Use barrier_nospec in syscall entry
Hi Michal,
Thanks for working on this series in the absence of any documentation.
Michal Suchánek <msuchanek@...e.de> writes:
> On Fri, 16 Mar 2018 15:18:23 +1000
> Nicholas Piggin <npiggin@...il.com> wrote:
>
>> On Thu, 15 Mar 2018 20:15:52 +0100
>> Michal Suchanek <msuchanek@...e.de> wrote:
>>
>> > On powerpc syscall entry is done in assembly so patch in an explicit
>> > barrier_nospec.
>>
>> Same comment as Linus for this -- the barriers are before the branch
>> here, so is it possible the branch instruction can be speculative
>> while the index is used to load the syscall table?
>
> As far as I understand barriers they separate code before the barrier
> and code after the barrier.
>
> So inserting barrier_nospec after cmpldi means that the result of the
> cmpldi has to be known before any instruction following barrier_nospec
> that depends on the result can be executed.
That would make sense, but I don't think that's how the barrier's been
defined.
I don't have a formal spec for it (yet), but what I do have indicates it
only orders older branches vs future instructions.
> However, you have probably knowledge of the powerpc implementation of
> the barrier so if the semantic is actually different then please
> enlighten me.
We have some knowledge, but only some :)
It's not necessarily implemented the same way on each chip revision, so
it's not entirely clear what the formal semantics will be vs what we are
seeing in current implementations. But I think it's safe to say it
should always go after the branch that might be speculatively executed.
Will try and get some better documentation for you.
cheers
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