linux-kernel - Re: [PATCH v5 1/3] x86/msr: Add AMD Core Perf Extension MSRs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <alpine.DEB.2.21.1803162022190.1509@nanos.tec.linutronix.de>
Date:   Fri, 16 Mar 2018 20:22:41 +0100 (CET)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Paolo Bonzini <pbonzini@...hat.com>
cc:     Radim Krcmar <rkrcmar@...hat.com>,
        Janakarajan Natarajan <Janakarajan.Natarajan@....com>,
        kvm@...r.kernel.org, Borislav Petkov <bp@...en8.de>,
        linux-kernel@...r.kernel.org, Ingo Molnar <mingo@...hat.com>,
        "H . Peter Anvin" <hpa@...or.com>, Len Brown <len.brown@...el.com>,
        Kyle Huey <me@...ehuey.com>,
        Tom Lendacky <thomas.lendacky@....com>
Subject: Re: [PATCH v5 1/3] x86/msr: Add AMD Core Perf Extension MSRs

On Fri, 16 Mar 2018, Paolo Bonzini wrote:

> On 06/03/2018 22:03, Radim Krcmar wrote:
> >>  /* Fam 15h MSRs */
> >>  #define MSR_F15H_PERF_CTL		0xc0010200
> >> +#define MSR_F15H_PERF_CTL0		MSR_F15H_PERF_CTL
> >> +#define MSR_F15H_PERF_CTL1		(MSR_F15H_PERF_CTL + 2)
> >> +#define MSR_F15H_PERF_CTL2		(MSR_F15H_PERF_CTL + 4)
> >> +#define MSR_F15H_PERF_CTL3		(MSR_F15H_PERF_CTL + 6)
> >> +#define MSR_F15H_PERF_CTL4		(MSR_F15H_PERF_CTL + 8)
> >> +#define MSR_F15H_PERF_CTL5		(MSR_F15H_PERF_CTL + 10)
> >> +
> >>  #define MSR_F15H_PERF_CTR		0xc0010201
> >> +#define MSR_F15H_PERF_CTR0		MSR_F15H_PERF_CTR
> >> +#define MSR_F15H_PERF_CTR1		(MSR_F15H_PERF_CTR + 2)
> >> +#define MSR_F15H_PERF_CTR2		(MSR_F15H_PERF_CTR + 4)
> >> +#define MSR_F15H_PERF_CTR3		(MSR_F15H_PERF_CTR + 6)
> >> +#define MSR_F15H_PERF_CTR4		(MSR_F15H_PERF_CTR + 8)
> >> +#define MSR_F15H_PERF_CTR5		(MSR_F15H_PERF_CTR + 10)
> >> +
> > x86 maintainers,
> > 
> > are you ok with this going through the kvm tree?

yes.

Acked-by: Thomas Gleixner <tglx@...utronix.de>