linux-kernel - Re: [PATCH v4 4/6] infiniband: cxgb4: Eliminate duplicate barriers on weakly-ordered archs

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Date:   Thu, 22 Mar 2018 20:45:11 +0000
From:   Casey Leedom <leedom@...lsio.com>
To:     Jason Gunthorpe <jgg@...pe.ca>
CC:     SWise OGC <swise@...ngridcomputing.com>,
        Sinan Kaya <okaya@...eaurora.org>,
        'kbuild test robot' <lkp@...el.com>,
        "kbuild-all@...org" <kbuild-all@...org>,
        "linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
        "timur@...eaurora.org" <timur@...eaurora.org>,
        "sulrich@...eaurora.org" <sulrich@...eaurora.org>,
        "linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Steve Wise <swise@...lsio.com>,
        "'Doug Ledford'" <dledford@...hat.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Michael Werner <werner@...lsio.com>
Subject: Re: [PATCH v4 4/6] infiniband: cxgb4: Eliminate duplicate barriers on
 weakly-ordered archs

Yes, but ...

For instance, I see that the x86 writel() has "memory" in its asm(), which
prevents GCC from reordering generated instructions.  And it ~looks like~
arm64 ~sort of~ gets that with the inclusion of __iowmb() (which translates
to wmb() then dsb(st) which finally holds the GCC "memory" barrier).  Is
this part of the documented semantic of the writel_relaxed()?  The PowerPC
stuff simply defines writel_relaxed() as writel() and I can't find the
bottom of that Rabbit Hole ...

I'm guessing~ that this line in the documentation ~may~ imply the GCC
ordering:

     ... Note that relaxed accesses to
     the same peripheral are guaranteed to be ordered with respect to each
     other. ...

In any case, we really only have a few places where we (the various Chelsio
drivers) need to worry about this: the "Fast Paths" where we have a lot of
I/O to the device.  I think we should leave everything else alone.

Casey