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Message-ID: <20180322212510.GE9469@ziepe.ca>
Date: Thu, 22 Mar 2018 15:25:10 -0600
From: Jason Gunthorpe <jgg@...pe.ca>
To: Casey Leedom <leedom@...lsio.com>
Cc: SWise OGC <swise@...ngridcomputing.com>,
Sinan Kaya <okaya@...eaurora.org>,
'kbuild test robot' <lkp@...el.com>,
"kbuild-all@...org" <kbuild-all@...org>,
"linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
"timur@...eaurora.org" <timur@...eaurora.org>,
"sulrich@...eaurora.org" <sulrich@...eaurora.org>,
"linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Steve Wise <swise@...lsio.com>,
'Doug Ledford' <dledford@...hat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Michael Werner <werner@...lsio.com>
Subject: Re: [PATCH v4 4/6] infiniband: cxgb4: Eliminate duplicate barriers
on weakly-ordered archs
On Thu, Mar 22, 2018 at 08:45:11PM +0000, Casey Leedom wrote:
> I'm guessing~ that this line in the documentation ~may~ imply the GCC
> ordering:
>
> ... Note that relaxed accesses to
> the same peripheral are guaranteed to be ordered with respect to each
> other. ...
An arch can't guarentee "ordered with respect to each other" without
preventing the compiler from re-ordering, so yes, any correct
implementation of writel_relaxed must prevent compiler re-ordering.
eg with volatile or a compiler barrier, or whatever.
> In any case, we really only have a few places where we (the various Chelsio
> drivers) need to worry about this: the "Fast Paths" where we have a lot of
> I/O to the device. I think we should leave everything else alone.
Yes.
Jason
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