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Message-ID: <201804040426.r7NS8aS0%fengguang.wu@intel.com>
Date: Wed, 4 Apr 2018 04:57:34 +0800
From: kbuild test robot <lkp@...el.com>
To: Matt Redfearn <matt.redfearn@...s.com>
Cc: kbuild-all@...org, James Hogan <jhogan@...nel.org>,
Ralf Baechle <ralf@...ux-mips.org>, linux-mips@...ux-mips.org,
Matt Redfearn <matt.redfearn@...s.com>,
Namhyung Kim <namhyung@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
linux-kernel@...r.kernel.org, Ingo Molnar <mingo@...hat.com>,
Jiri Olsa <jolsa@...hat.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>
Subject: Re: [PATCH 5/5] MIPS: perf: Fold vpe_id() macro into it's one last
usage
Hi Matt,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/perf/core]
[also build test ERROR on v4.16 next-20180403]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Matt-Redfearn/MIPS-perf-MT-fixes-and-improvements/20180404-011026
config: mips-gpr_defconfig (attached as .config)
compiler: mipsel-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=mips
All errors (new ones prefixed by >>):
In file included from include/linux/kernel.h:14:0,
from include/linux/cpumask.h:10,
from arch/mips/kernel/perf_event_mipsxx.c:18:
arch/mips/kernel/perf_event_mipsxx.c: In function 'mipsxx_pmu_free_counter':
arch/mips/kernel/perf_event_mipsxx.c:353:42: error: 'cpu' undeclared (first use in this function)
pr_debug("CPU%d released counter %d\n", cpu, hwc->idx);
^
include/linux/printk.h:136:17: note: in definition of macro 'no_printk'
printk(fmt, ##__VA_ARGS__); \
^~~~~~~~~~~
arch/mips/kernel/perf_event_mipsxx.c:353:2: note: in expansion of macro 'pr_debug'
pr_debug("CPU%d released counter %d\n", cpu, hwc->idx);
^~~~~~~~
arch/mips/kernel/perf_event_mipsxx.c:353:42: note: each undeclared identifier is reported only once for each function it appears in
pr_debug("CPU%d released counter %d\n", cpu, hwc->idx);
^
include/linux/printk.h:136:17: note: in definition of macro 'no_printk'
printk(fmt, ##__VA_ARGS__); \
^~~~~~~~~~~
arch/mips/kernel/perf_event_mipsxx.c:353:2: note: in expansion of macro 'pr_debug'
pr_debug("CPU%d released counter %d\n", cpu, hwc->idx);
^~~~~~~~
arch/mips/kernel/perf_event_mipsxx.c: In function 'mipsxx_pmu_enable_event':
>> arch/mips/kernel/perf_event_mipsxx.c:372:25: error: 'cpu_has_mipsmt_pertccounters' undeclared (first use in this function); did you mean 'can_use_mips_counter'?
unsigned int vpe_id = cpu_has_mipsmt_pertccounters ? 0 :
^~~~~~~~~~~~~~~~~~~~~~~~~~~~
can_use_mips_counter
arch/mips/kernel/perf_event_mipsxx.c:376:22: error: expected expression before ')' token
} else if (range > V) {
^
arch/mips/kernel/perf_event_mipsxx.c: In function 'mipspmu_perf_event_encode':
arch/mips/kernel/perf_event_mipsxx.c:708:28: error: 'const struct mips_perf_event' has no member named 'range'
return ((unsigned int)pev->range << 24) |
^~
vim +372 arch/mips/kernel/perf_event_mipsxx.c
327
328 static void mipsxx_pmu_free_counter(struct cpu_hw_events *cpuc,
329 struct hw_perf_event *hwc)
330 {
331 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
332 int sibling_cpu, cpu = smp_processor_id();
333
334 /* When counters are per-core, free them in all sibling CPUs */
335 if (!cpu_has_mipsmt_pertccounters) {
336 struct cpu_hw_events *sibling_cpuc;
337 unsigned long flags;
338
339 spin_lock_irqsave(&core_counters_lock, flags);
340
341 for_each_cpu(sibling_cpu, &cpu_sibling_map[cpu]) {
342 sibling_cpuc = per_cpu_ptr(&cpu_hw_events, sibling_cpu);
343
344 clear_bit(hwc->idx, sibling_cpuc->used_mask);
345 pr_debug("CPU%d released core counter %d\n",
346 sibling_cpu, hwc->idx);
347 }
348
349 spin_unlock_irqrestore(&core_counters_lock, flags);
350 return;
351 }
352 #endif
> 353 pr_debug("CPU%d released counter %d\n", cpu, hwc->idx);
354 clear_bit(hwc->idx, cpuc->used_mask);
355 }
356
357 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
358 {
359 struct perf_event *event = container_of(evt, struct perf_event, hw);
360 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
361 unsigned int range = evt->event_base >> 24;
362
363 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
364
365 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
366 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
367 /* Make sure interrupt enabled. */
368 MIPS_PERFCTRL_IE;
369
370 if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) {
371 /* enable the counter for the calling thread */
> 372 unsigned int vpe_id = cpu_has_mipsmt_pertccounters ? 0 :
373 (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK);
374
375 cpuc->saved_ctrl[idx] |= BIT(12 + vpe_id) | BRCM_PERFCTRL_TC;
376 } else if (range > V) {
377 /* The counter is processor wide. Set it up to count all TCs. */
378 pr_debug("Enabling perf counter for all TCs\n");
379 cpuc->saved_ctrl[idx] |= M_TC_EN_ALL;
380 } else {
381 unsigned int cpu, ctrl;
382
383 /*
384 * Set up the counter for a particular CPU when event->cpu is
385 * a valid CPU number. Otherwise set up the counter for the CPU
386 * scheduling this thread.
387 */
388 cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id();
389
390 ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu]));
391 ctrl |= M_TC_EN_VPE;
392 cpuc->saved_ctrl[idx] |= ctrl;
393 pr_debug("Enabling perf counter for CPU%d\n", cpu);
394 }
395 /*
396 * We do not actually let the counter run. Leave it until start().
397 */
398 }
399
---
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