Message-ID: <CAK8P3a2rC3jymPDJbpxsYZRYMAcSJy6zXjYrxKPHrGxj63vBtg@mail.gmail.com>
Date:   Tue, 10 Apr 2018 13:29:53 +0200
From:   Arnd Bergmann <arnd@...db.de>
To:     Benjamin Herrenschmidt <benh@...nel.crashing.org>
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Andrew Jeffery <andrew@...id.au>,
        Joel Stanley <joel.stanley@....ibm.com>,
        Jeremy Kerr <jeremy.kerr@....ibm.com>
Subject: Re: How to expose various BMC chip controls ?

On Tue, Apr 10, 2018 at 11:17 AM, Benjamin Herrenschmidt
<benh@...nel.crashing.org> wrote:
> Hi Folks !
>
> I would like to discuss something we need to solve for BMC chips before
> we start implementing a solution that you'll reject upstream :-)
>
> So quick recap: the BMC chip is the management controller of your
> server, typically some kind of specialized ARM SoC which controls a
> variety of things ranging from power supply, fans, inventory, flash, to
> having even a built-in GPU connected to the main server processor via
> PCIe etc...
>
> As part of the OpenBMC project, we have been contributing (along with
> others from Google etc...) a bunch of upstream drivers to support the
> BMC chips from Aspeed which are quite popular. There's work in progress
> to also upstream other vendor(s) chip support.
>
> For most things, we can write appropriate drivers.
>
> However, there's a range of things for which there is no good fit for
> dedicated per-function kernel drivers in the BMC:
>
> The BMC chips have a variety of control bits and pieces (registers)
> that affect the host in all sorts of ways. A few semi-random examples:
>
>  - Scratch registers that the host BIOS can read via LPC that contain
> system specific details of interest to the BIOS itself. The
> content/format is specific to a given BIOS <-> BMC userspace pair.
>
>  - Similar ones related to the built-in VGA (the one the host sees on
> PCIe, it doesn't appear as a device on the BMC side). Used to pass some
> wiring information to the VGA BIOS and the Linux driver among others.
>
>  - Bits controlling which parts of the BMC the host can access remotely
> via either LPC or PCIe. (Visibility of the VGA to the host, of the BMC
> PCIe system-controller device, opening of various windows from the host
> into the BMC address space etc...)
>
>  - ... and a few more
>
> Those things tend to be fairly system specific. Meaning that what's
> written in them (or read from them) and when it's written in these
> registers should be under userspace control on the BMC. There isn't
> necessarily many registers that need to be exposed that way, here too,
> which specific ones is rather system specific.
>
> But /dev/mem isn't a solution :-)
>
> So one simple idea I had, you tell me if it can fly, is to have some
> driver for the SoC as a whole (thinking of syscon here...) expose a
> selection of these things via sysfs.
>
> The list being potentially system specific, it would be provided to
> the kernel via the device-tree (binding tbd) where we would effectively
> provide a list of names, register offset, start bit, bitfield size.
>
> Any better idea ? It's a fairly simple problem, and the above solution
> would be very little code, but I just don't want us to go down a rabbit
> hole if some of you have religious objections to some of it :)

I think the hard part is finding the right balance: traditionally, these
kinds of systems used ad-hoc interfaces like /dev/mem or random
kernel interfaces to do both very generic and very non-generic
thigns.

The initial reaction you get when posting a patch that adds
an ad-hoc interface will (should?) always be a question of "can
this be done using a generic interface?", but that doesn't mean
that the answer is always "yes", we just need to come up with
ideas of how that interface would look like and figure out together
if it's actually worth it or not.

In the cases where an ad-hoc interface is needed, I can see
two options: we can stick something in drivers/soc that exposes
it in the least ugly way, completely specific to that particular
SoC, or we can create a new subsystem from "random BMC
slave-side interfaces" and have it maintained by you all (leave
me out of the picture, except if you are looking for ideas).

In any case, I think it makes most sense to discuss new interfaces
between the people working on the competing BMC implementations,
mainly to see if some functionality can be abstracted in a common
way or not. I believe you are already working with the Nuvoton BMC
people, but I don't know much about the others. Is the
Emulex/Broadcom/Aspeed "Pilot" BMC series used anywhere
that you know of? It seems that Renesas and TI are no longer
active in this space, and that the big server vendors are either
not running Linux (e.g. HP) on their BMC or they have their
own software stack on the generic third-party BMCs (e.g. Dell).
I think Huawei also has their own BMC hardware, but no idea
what they run on it. Do you know of any others?

       Arnd

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