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Message-ID: <CAJKOXPcWQUHHhf2gV3u4fu=wuVf3qxOYwNdj0c_JFc+zqfJUkA@mail.gmail.com> Date: Wed, 11 Apr 2018 11:52:44 +0200 From: Krzysztof Kozlowski <krzk@...nel.org> To: Tomasz Figa <tomasz.figa@...il.com> Cc: Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>, Sylwester Nawrocki <s.nawrocki@...sung.com>, "linus.walleij@...aro.org" <linus.walleij@...aro.org>, Kukjin Kim <kgene@...nel.org>, linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>, "moderated list:SAMSUNG SOC CLOCK DRIVERS" <linux-samsung-soc@...r.kernel.org>, linux-gpio@...r.kernel.org, linux-kernel <linux-kernel@...r.kernel.org>, Marek Szyprowski <m.szyprowski@...sung.com> Subject: Re: [PATCH] pinctrl/samsung: Correct EINTG banks order On Wed, Apr 11, 2018 at 10:36 AM, Tomasz Figa <tomasz.figa@...il.com> wrote: > 2018-04-10 17:38 GMT+09:00 Tomasz Figa <tomasz.figa@...il.com>: >> 2018-04-10 16:06 GMT+09:00 Krzysztof Kozlowski <krzk@...nel.org>: >>> On Sun, Apr 8, 2018 at 8:07 PM, Paweł Chmiel >>> <pawel.mikolaj.chmiel@...il.com> wrote: >>>> All banks with GPIO interrupts should be at beginning >>>> of bank array and without any other types of banks between them. >>>> This order is expected by exynos_eint_gpio_irq, when doing >>>> interrupt group to bank translation. >>>> Otherwise, kernel NULL pointer dereference would happen >>>> when trying to handle interrupt, due to wrong bank being looked up. >>>> Observed on s5pv210, when trying to handle gpj0 interrupt, >>>> where kernel was mapping it to gpi bank. >>> >>> Thanks for the patch. The issue looks real although one thing was >>> missed - there is a gap in SVC group between GPK2 and GPL0 (pointed by >>> Marek Szyprowski): >>> >>> 0x0 - EINT_23 - gpk0 >>> 0x1 - EINT_24 - gpk1 >>> 0x2 - EINT_25 - gpk2 >>> 0x4 - EINT_27 - gpl0 >>> 0x7 - EINT_8 - gpm0 >>> >>> Maybe this should be done differently - to remove such hidden >>> requirement entirely in favor of another parameter of >>> EXYNOS_PIN_BANK_EINTG argument? >> >> Perhaps let's limit this patch to s5pv210 and Exynos5410 alone, where >> a simple swap of bank order in the arrays should be okay. >> >> We might also need to have some fixes on 4x12, because I noticed that >> in exynos4x12_pin_banks0[] there is a hole in eint_offsets between >> gpd1 and gpf0 and exynos4x12_pin_banks1[] starts with gpk0 that has >> eint_offset equal to 0x08 (not 0). > > To close the loop, after talking offline and checking the > documentation, Exynos4x12 is fine, because the group numbers in SVC > register actually match what is defined in bank arrays. Great! Thanks for checking. Best regards, Krzysztof
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