linux-kernel - Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

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Message-ID: <20180412215149.GA27802@saruman>
Date:   Thu, 12 Apr 2018 22:51:50 +0100
From:   James Hogan <jhogan@...nel.org>
To:     Sinan Kaya <okaya@...eaurora.org>
Cc:     linux-mips@...ux-mips.org, arnd@...db.de, timur@...eaurora.org,
        sulrich@...eaurora.org, linux-arm-msm@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        Ralf Baechle <ralf@...ux-mips.org>,
        Paul Burton <paul.burton@...s.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in
 readX()

On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote:
> While a barrier is present in writeX() function before the register write,
> a similar barrier is missing in the readX() function after the register
> read. This could allow memory accesses following readX() to observe
> stale data.
> 
> Signed-off-by: Sinan Kaya <okaya@...eaurora.org>
> Reported-by: Arnd Bergmann <arnd@...db.de>

Both patches look like obvious improvements to me, so I'm happy to apply
to my fixes branch.

I'm guessing the case of a write to DMA buffer (i.e. reusing it) after a
MMIO readX() (checking DMA complete) being visible to DMA reads prior to
the readX() is precluded by a control dependency (you shouldn't reuse
buffer until you've checked DMA is complete).

But why don't we always use wmb() in the writeX() case? Might not the
cached write to DMA buffer be reordered with the uncached write to MMIO
register from the coherent DMA point of view? I'm waiting on feedback
from MIPS hardware folk on this topic.

Cheers
James

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