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Message-ID: <33c9c074-e0a5-7552-9993-269cd85101aa@codeaurora.org>
Date: Thu, 12 Apr 2018 18:38:39 -0400
From: Sinan Kaya <okaya@...eaurora.org>
To: James Hogan <jhogan@...nel.org>
Cc: linux-mips@...ux-mips.org, arnd@...db.de, timur@...eaurora.org,
sulrich@...eaurora.org, linux-arm-msm@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paul.burton@...s.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in
readX()
On 4/12/2018 5:58 PM, James Hogan wrote:
> On Thu, Apr 12, 2018 at 10:51:49PM +0100, James Hogan wrote:
>> On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote:
>>> While a barrier is present in writeX() function before the register write,
>>> a similar barrier is missing in the readX() function after the register
>>> read. This could allow memory accesses following readX() to observe
>>> stale data.
>>>
>>> Signed-off-by: Sinan Kaya <okaya@...eaurora.org>
>>> Reported-by: Arnd Bergmann <arnd@...db.de>
>>
>> Both patches look like obvious improvements to me, so I'm happy to apply
>> to my fixes branch.
>
> Though having said that, a comment to go with the rmb() (as suggested by
> checkpatch) to detail the situation we're concerned about would be nice
> to have.
I can send a new version. No worries.
Functional correctness is more important at this moment. I can accommodate
any nice to haves.
>
> Cheers
> James
>
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
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