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Message-ID: <e978fa34-d9a6-281c-6620-c9d10c7b54ae@codeaurora.org>
Date: Fri, 13 Apr 2018 12:30:09 +0530
From: Manu Gautam <mgautam@...eaurora.org>
To: Stephen Boyd <sboyd@...nel.org>,
Doug Anderson <dianders@...omium.org>
Cc: Kishon Vijay Abraham I <kishon@...com>,
Rob Herring <robh@...nel.org>,
Stephen Boyd <sboyd@...eaurora.org>,
LKML <linux-kernel@...r.kernel.org>, devicetree@...r.kernel.org,
Rob Herring <robh+dt@...nel.org>,
Vivek Gautam <vivek.gautam@...eaurora.org>,
Evan Green <evgreen@...omium.org>,
linux-arm-msm@...r.kernel.org,
Varadarajan Narayanan <varada@...eaurora.org>,
Wei Yongjun <weiyongjun1@...wei.com>,
Fengguang Wu <fengguang.wu@...el.com>
Subject: Re: [PATCH v4 2/7] phy: qcom-qmp: Enable pipe_clk before PHY
initialization
Hi,
On 4/13/2018 2:08 AM, Stephen Boyd wrote:
> Quoting Manu Gautam (2018-04-11 08:37:38)
>>> I ask because it may be easier to never expose these clks in Linux, hit
>>> the enable bits in the branches during clk driver probe, and then act
>>> like they never exist because we don't really use them.
>> This sounds better idea. Let me check if I can get a patch for same in msm8996
>> and sdm845 clock drivers.
>>
> Ok! Presumably the PHY has a way to tell if it failed to turn on right?
> Put another way, I'm hoping these branch bits aren't there to help us
> debug and figure out when the PHY PLL fails to lock.
Yes, PHY has a PCS_STATUS3 register that indicates whether pipe_clk got enabled or
not.
--
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