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Date: Fri, 27 Apr 2018 18:00:22 +0530 From: Chintan Pandya <cpandya@...eaurora.org> To: Catalin Marinas <catalin.marinas@....com> Cc: will.deacon@....com, mark.rutland@....com, toshi.kani@....com, linux-arch@...r.kernel.org, arnd@...db.de, ard.biesheuvel@...aro.org, marc.zyngier@....com, gregkh@...uxfoundation.org, linux-kernel@...r.kernel.org, kristina.martsenko@....com, takahiro.akashi@...aro.org, james.morse@....com, tglx@...utronix.de, akpm@...ux-foundation.org, linux-arm-kernel@...ts.infradead.org Subject: Re: [PATCH v8 2/4] arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable On 4/27/2018 3:59 PM, Catalin Marinas wrote: > On Tue, Apr 03, 2018 at 01:30:44PM +0530, Chintan Pandya wrote: >> Add an interface to invalidate intermediate page tables >> from TLB for kernel. >> >> Signed-off-by: Chintan Pandya <cpandya@...eaurora.org> >> --- >> arch/arm64/include/asm/tlbflush.h | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h >> index 9e82dd7..6a4816d 100644 >> --- a/arch/arm64/include/asm/tlbflush.h >> +++ b/arch/arm64/include/asm/tlbflush.h >> @@ -209,6 +209,12 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, >> dsb(ish); >> } >> >> +static inline void __flush_tlb_kernel_pgtable(unsigned long addr) >> +{ >> + addr >>= 12; >> + __tlbi(vaae1is, addr); >> + dsb(ish); >> +} >> #endif > > Please use __TLBI_VADDR here as it does some additional masking. > Sure. Chintan -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
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