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Message-ID: <8b7e4588-5a35-6c18-fe60-148d6ccf778c@ti.com>
Date:   Tue, 1 May 2018 15:23:31 +0530
From:   Sekhar Nori <nsekhar@...com>
To:     Bartosz Golaszewski <brgl@...ev.pl>,
        Kevin Hilman <khilman@...nel.org>,
        Russell King <linux@...linux.org.uk>,
        Boris Brezillon <boris.brezillon@...tlin.com>,
        Richard Weinberger <richard@....at>,
        David Woodhouse <dwmw2@...radead.org>,
        Brian Norris <computersforpeace@...il.com>,
        Marek Vasut <marek.vasut@...il.com>,
        Tony Lindgren <tony@...mide.com>,
        Krzysztof Kozlowski <krzk@...nel.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-mtd@...ts.infradead.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>
Subject: Re: [PATCH 01/12] mtd: nand: davinci: store the core chipselect
 number in platform data

On Tuesday 01 May 2018 02:55 PM, Sekhar Nori wrote:
> On Monday 30 April 2018 01:54 PM, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski <bgolaszewski@...libre.com>
>>
>> We have the 'ti,davinci-chipselect' property in the device tree, but
>> when using platform data the driver silently uses the id field of
>> struct platform_device as the chipselect. This is confusing and we
>> almost broke the nand support again recently after converting the
>> platform to common clock framework (which changed the device id in the
>> clock lookup - the problem is gone now that we no longer acquire the
>> clock in the nand driver.
>>
>> This patch adds a new filed - core_chipsel - to the platform_data.
> 
> s/filed/field
> 
>> Subsequent patches will convert the platforms to using this new field.
> 
> Can you add a comment for this new field too, like how we have for most
> other fields?
> 
> Curious on what 'core' in core_chipsel means. Something to do with
> chip-select offset we have on DA850?

Looks like you may have just picked the terminology from DaVinci NAND
driver (introduced back in 2009). But in this context, it means the
0-indexed chip-select number that of the asynchronous memory interface
to which the NAND device is connected.

So, may be a comment here will suffice.

Thanks,
Sekhar

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