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Message-ID: <825117a7-0412-0558-f7e0-37e026b45db2@gmail.com>
Date: Thu, 10 May 2018 12:19:23 +0200
From: Marek Vasut <marek.vasut@...il.com>
To: Tudor Ambarus <tudor.ambarus@...rochip.com>,
Cyrille Pitchen <cyrille.pitchen@...rochip.com>,
dwmw2@...radead.org, computersforpeace@...il.com,
boris.brezillon@...tlin.com, richard@....at
Cc: linux-mtd@...ts.infradead.org, LKML <linux-kernel@...r.kernel.org>,
Nicolas Ferre <nicolas.ferre@...rochip.com>
Subject: Re: support for non-uniform SPI NOR flash memories
On 05/09/2018 06:40 PM, Tudor Ambarus wrote:
>
> On 05/07/2018 08:14 PM, Marek Vasut wrote:
>> But indeed there are -- to my knowledge -- no flashes with interleaved
>> erase blocks. And yes, there could be improvement in erasing exactly the
>> required chunk of flash with a fitting opcode:)
>
> Thanks Marek.
>
> Other improvement would be to minimize the amount of erase() calls by
> using the best sequence of erase type commands depending on alignment.
> But this will increase the number of queries.
>
> I've read again the Sector Map section of the JEDECB standard and it
> looks like "overlaid" regions are possible. Here's an example that I
> found there:
>
> Bottom: 8x 4KB sectors at bottom (only 4KB erase supported),
> 1x overlaid 64KB sector at bottom (only 64KB erase supported),
> 511 uniform 64KB sectors (only 64KB erase supported)
>
> That's interesting, when one wants to erase the overlaid 64KB sector, I
> guess that the 8x 4KB sectors will be erased too.
Ah yes, some old flashes had these few 64 kiB erase blocks at the
beginning/end, which could either be erased as one 64 kiB block or as
smaller 8k/4k blocks .
> I'm still studying this, I'll try to come with a proposal in the next
> few days.
Cool!
--
Best regards,
Marek Vasut
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