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Message-ID: <7bed6350-b6ee-1d79-39f5-bf0db2c2b102@gmail.com>
Date: Sat, 2 Jun 2018 14:00:18 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Stephen Boyd <sboyd@...nel.org>,
Jonathan Hunter <jonathanh@...dia.com>,
Michael Turquette <mturquette@...libre.com>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Thierry Reding <thierry.reding@...il.com>
Cc: Mark Rutland <mark.rutland@....com>,
Rob Herring <robh+dt@...nel.org>, linux-tegra@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 3/4] clk: tegra20: Turn EMC clock gate into divider
On 02.06.2018 09:37, Stephen Boyd wrote:
> Quoting Dmitry Osipenko (2018-05-30 08:06:45)
>> Kernel should never gate the EMC clock as it causes immediate lockup, so
>> removing clk-gate functionality doesn't affect anything. Turning EMC clk
>> gate into divider allows to implement glitch-less EMC scaling, avoiding
>> reparenting to a backup clock.
>>
>> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
>
> Looks ok to me, but I'm waiting for someone from Tegra side to ack it or
> review it.
>
I've already prepared v2 with some minor cleanups and additional clk patch. For
now waiting for Peter's review comments to v1.
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