linux-kernel - RE: [PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs

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Message-ID: <82D7661F83C1A047AF7DC287873BF1E167FEFFF6@SHSMSX101.ccr.corp.intel.com>
Date:   Fri, 8 Jun 2018 14:26:08 +0000
From:   "Kang, Luwei" <luwei.kang@...el.com>
To:     Alexander Shishkin <alexander.shishkin@...ux.intel.com>
CC:     "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
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        "thomas.lendacky@....com" <thomas.lendacky@....com>,
        "bp@...e.de" <bp@...e.de>, "Liang, Kan" <kan.liang@...el.com>,
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Subject: RE: [PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for
 Intel PT MSRs

> > These bit definitions are use for emulate MSRs read/write for KVM. For
> > example, IA32_RTIT_CTL.FabricEn[bit 6] is available only when
> > CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest try to set this
> > bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0 a #GP would be injected
> > to KVM guest.
> 
> Do we have anything in the guest that this feature will work with?
> 

It depend on PT driver. KVM need to do some security check if kvm guest (maybe linux or other os) try to set any bits of these MSRs.

Thanks,
Luwei Kang