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Message-ID: <20180609075256.725354d6@bbrezillon>
Date: Sat, 9 Jun 2018 07:52:56 +0200
From: Boris Brezillon <boris.brezillon@...tlin.com>
To: Stefan Agner <stefan@...er.ch>
Cc: Dmitry Osipenko <digetx@...il.com>, dwmw2@...radead.org,
computersforpeace@...il.com, marek.vasut@...il.com,
robh+dt@...nel.org, mark.rutland@....com, thierry.reding@...il.com,
dev@...xeye.de, miquel.raynal@...tlin.com, richard@....at,
marcel@...wiler.com, krzk@...nel.org, benjamin.lindqvist@...ian.se,
jonathanh@...dia.com, pdeschrijver@...dia.com, pgaikwad@...dia.com,
mirza.krak@...il.com, linux-mtd@...ts.infradead.org,
linux-tegra@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash
controller driver
On Fri, 08 Jun 2018 23:51:01 +0200
Stefan Agner <stefan@...er.ch> wrote:
> >
> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
> > {
> > int err;
> >
> > disable_irq(ctrl->irq);
> >
> > err = reset_control_reset(ctrl->rst);
> > if (err) {
> > dev_err(ctrl->dev, "Failed to reset HW: %d\n", err);
> > msleep(HW_TIMEOUT);
> > }
> >
> > writel_relaxed(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD);
> > writel_relaxed(HWSTATUS_MASK, ctrl->regs + HWSTATUS_MASK);
> > writel_relaxed(INT_MASK, ctrl->regs + ISR);
>
> If we do a controller reset, there is much more state than that which
> needs to be restored. A lot of it is not readily available currently
> (timing, ECC settings...)
This is actually a good test to detect what is not properly initialized
by the driver. Timings should be configured correctly through
->setup_data_interface(). ECC engine should be disabled by default and
only enabled when ->{read,write}_page() is called.
>
> That seems a lot of work for a code path I do not intend to ever use :-)
>
Not so sure it's a lot of work. If ECC and timing settings are the
only thing you need to initialize then it should work just fine.
Try with a controller reset and you'll know if you miss something ;-).
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