linux-kernel - Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

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Message-ID: <20180609084157.0c2f12e6@bbrezillon>
Date:   Sat, 9 Jun 2018 08:41:57 +0200
From:   Boris Brezillon <boris.brezillon@...tlin.com>
To:     Stefan Agner <stefan@...er.ch>
Cc:     Dmitry Osipenko <digetx@...il.com>, dwmw2@...radead.org,
        computersforpeace@...il.com, marek.vasut@...il.com,
        robh+dt@...nel.org, mark.rutland@....com, thierry.reding@...il.com,
        dev@...xeye.de, miquel.raynal@...tlin.com, richard@....at,
        marcel@...wiler.com, krzk@...nel.org, benjamin.lindqvist@...ian.se,
        jonathanh@...dia.com, pdeschrijver@...dia.com, pgaikwad@...dia.com,
        mirza.krak@...il.com, linux-mtd@...ts.infradead.org,
        linux-tegra@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash
 controller driver

On Sat, 09 Jun 2018 08:23:51 +0200
Stefan Agner <stefan@...er.ch> wrote:

> On 09.06.2018 07:52, Boris Brezillon wrote:
> > On Fri, 08 Jun 2018 23:51:01 +0200
> > Stefan Agner <stefan@...er.ch> wrote:
> > 
> >   
> >> >
> >> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
> >> > {
> >> > 	int err;
> >> >
> >> > 	disable_irq(ctrl->irq);
> >> >
> >> > 	err = reset_control_reset(ctrl->rst);
> >> > 	if (err) {
> >> > 		dev_err(ctrl->dev, "Failed to reset HW: %d\n", err);
> >> > 		msleep(HW_TIMEOUT);
> >> > 	}
> >> >
> >> > 	writel_relaxed(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD);
> >> > 	writel_relaxed(HWSTATUS_MASK, ctrl->regs + HWSTATUS_MASK);
> >> > 	writel_relaxed(INT_MASK, ctrl->regs + ISR);  
> >>
> >> If we do a controller reset, there is much more state than that which
> >> needs to be restored. A lot of it is not readily available currently
> >> (timing, ECC settings...)  
> > 
> > This is actually a good test to detect what is not properly initialized
> > by the driver. Timings should be configured correctly through  
> > ->setup_data_interface(). ECC engine should be disabled by default and  
> > only enabled when ->{read,write}_page() is called.
> >   
> 
> Is setup_data_interface guaranteed to be called after a failed
> ->exec_op()/{read,write}_page()?

No. Maybe I misunderstood when tegra_nand_controller_reset() was
supposed to be called. That's something I would call only once, early
in the probe function, so that the controller is placed in a well-known
state before we start using it. Definitely not something you should
call after each error.

> 
> >>
> >> That seems a lot of work for a code path I do not intend to ever use :-)
> >>  
> > 
> > Not so sure it's a lot of work. If ECC and timing settings are the
> > only thing you need to initialize then it should work just fine.
> > Try with a controller reset and you'll know if you miss something ;-).  
> 
> Currently the setting gets written directly to the registers. Only the
> enable flag is set in the HW ECC {read,write}_page() functions. So I
> will have to store the complete register in the chip structure and write
> them on every {read,write}_page()?

Well, your solution works as long as you only have one chip connected
to the controller. What we usually set the ECC config in
->select_chip() (or at least make sure the current setting matches the
one we expect) and then enable the engine in read/write_page() (as you
seem to already do).