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Message-ID: <1528729376.4526.0.camel@2b52.sc.intel.com>
Date: Mon, 11 Jun 2018 08:02:56 -0700
From: Yu-cheng Yu <yu-cheng.yu@...el.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Andy Lutomirski <luto@...nel.org>,
LKML <linux-kernel@...r.kernel.org>, linux-doc@...r.kernel.org,
Linux-MM <linux-mm@...ck.org>,
linux-arch <linux-arch@...r.kernel.org>, X86 ML <x86@...nel.org>,
"H. Peter Anvin" <hpa@...or.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. J. Lu" <hjl.tools@...il.com>,
"Shanbhogue, Vedvyas" <vedvyas.shanbhogue@...el.com>,
"Ravi V. Shankar" <ravi.v.shankar@...el.com>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Jonathan Corbet <corbet@....net>,
Oleg Nesterov <oleg@...hat.com>, Arnd Bergmann <arnd@...db.de>,
mike.kravetz@...cle.com
Subject: Re: [PATCH 02/10] x86/cet: Introduce WRUSS instruction
On Mon, 2018-06-11 at 10:17 +0200, Peter Zijlstra wrote:
> On Thu, Jun 07, 2018 at 09:40:02AM -0700, Andy Lutomirski wrote:
> > On Thu, Jun 7, 2018 at 7:41 AM Yu-cheng Yu <yu-cheng.yu@...el.com> wrote:
>
> > Peterz, isn't there some fancy better way we're supposed to handle the
> > error return these days?
>
> > > + asm volatile("1:.byte 0x66, 0x0f, 0x38, 0xf5, 0x37\n"
> > > + "xor %[err],%[err]\n"
> > > + "2:\n"
> > > + ".section .fixup,\"ax\"\n"
> > > + "3: mov $-1,%[err]; jmp 2b\n"
> > > + ".previous\n"
> > > + _ASM_EXTABLE(1b, 3b)
> > > + : [err] "=a" (err)
> > > + : [val] "S" (val), [addr] "D" (addr)
> > > + : "memory");
>
> So the alternative is something like:
>
> __visible bool ex_handler_wuss(const struct exception_table_entry *fixup,
> struct pt_regs *regs, int trapnr)
> {
> regs->ip = ex_fixup_addr(fixup);
> regs->ax = -1L;
>
> return true;
> }
>
>
> int err = 0;
>
> asm volatile("1: INSN_WUSS\n"
> "2:\n"
> _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wuss)
> : "=a" (err)
> : "S" (val), "D" (addr));
>
> But I'm not at all sure that's actually better.
Thanks! I will fix it.
Yu-cheng
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