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Message-ID: <CAHp75VcZgdgwQsNhomvsCy1p_X33MvbcAFpBY2s+SCyL5tbM=Q@mail.gmail.com>
Date: Wed, 13 Jun 2018 19:40:46 +0300
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com>
Cc: "Box, David E" <david.e.box@...el.com>,
Vishwanath Somayaji <vishwanath.somayaji@...el.com>,
Darren Hart <dvhart@...radead.org>,
Andy Shevchenko <andy@...radead.org>,
kyle.d.pelton@...ux.intel.com,
Platform Driver <platform-driver-x86@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [V3] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers
On Wed, Jun 13, 2018 at 5:07 PM, Rajneesh Bhardwaj
<rajneesh.bhardwaj@...el.com> wrote:
> On Fri, Jun 08, 2018 at 05:02:37PM -0700, Box, David E wrote:
>
> I am ok with the design and approach and also verified it on a Cannonlake
> system. I wont insist for a V4 unless Andy feels a need for respin but there
> are minor things that were missed.
> Also ISCLK_OC / ISCLK_MAIN suggestion is missing.
I missed this in discussion, so, please send v4 with settled fixes.
Meanwhile I keep v3 in my review and testing queue, thanks!
--
With Best Regards,
Andy Shevchenko
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