Message-ID: <20180618211536.0bf44f55@bbrezillon>
Date:   Mon, 18 Jun 2018 21:15:36 +0200
From:   Boris Brezillon <boris.brezillon@...tlin.com>
To:     Yogesh Narayan Gaur <yogeshnarayan.gaur@....com>
Cc:     Fabio Estevam <fabio.estevam@....com>,
        David Wolfe <david.wolfe@....com>,
        "dwmw2@...radead.org" <dwmw2@...radead.org>,
        "richard@....at" <richard@....at>,
        Prabhakar Kushwaha <prabhakar.kushwaha@....com>,
        Han Xu <han.xu@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
        "marek.vasut@...il.com" <marek.vasut@...il.com>,
        Frieder Schrempf <frieder.schrempf@...eet.de>,
        "broonie@...nel.org" <broonie@...nel.org>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        "miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
        "computersforpeace@...il.com" <computersforpeace@...il.com>
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI
 controller

Hi Yogesh,

On Mon, 18 Jun 2018 13:32:27 +0000
Yogesh Narayan Gaur <yogeshnarayan.gaur@....com> wrote:

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@...tlin.com] 
> Sent: Friday, June 15, 2018 7:26 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@....com>; Fabio Estevam <fabio.estevam@....com>; David Wolfe <david.wolfe@....com>; dwmw2@...radead.org
> Cc: richard@....at; Prabhakar Kushwaha <prabhakar.kushwaha@....com>; Han Xu <han.xu@....com>; linux-kernel@...r.kernel.org; linux-spi@...r.kernel.org; marek.vasut@...il.com; Frieder Schrempf <frieder.schrempf@...eet.de>; broonie@...nel.org; linux-mtd@...ts.infradead.org; miquel.raynal@...tlin.com; computersforpeace@...il.com
> Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller
> 
> On Fri, 15 Jun 2018 13:42:12 +0000
> Yogesh Narayan Gaur <yogeshnarayan.gaur@....com> wrote:
> 
> > Hi Boris,
> > 
> > I am still debugging the issue.
> > With some analysis, able to check that proper values are not being written for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.
> > 
> > In current code, value of map_addr are being assigned to these register.
> >              map_addr = q->memmap_phy +
> >                         2 * q->devtype_data->ahb_buf_size;
> > 
> >      qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
> > 
> > But instead of "q->devtype_data->ahb_buf_size" it should be flash size.  
> 
> No, because we're only using 2 * ->ahb_buf_size in the direct mapping for each device, and we're modifying the mapping dynamically based on the selected device. Maybe we got the logic wrong though.
> 
> Yes, for register QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD, we need to save starting actual address from where this flash is getting started.
> Thus, if my first flash size is 64MB, then register QUADSPI_SFA2AD would have value of q->memmap_phy + 0x4000000 i.e. (QUADSPI_SFA1AD + sizeof First Flash)
> If second flash is of size 32MB, then register QUADSPI_SFB1AD would have value of value of QUADSPI_SFA2AD + sizeof second flash.

Again, no, that's not what I'm trying to do, and the fact that it
worked fine with CS0 makes me think you don't need to map the whole
device to get it to work, just 2 * ->ahb_buf_size per device.

> 
> > For my case flash size is 0x4000000 and with this hard coded value I am able to perform Write and Erase operation.
> > One more change, I have to do is adding the flash_size when writing the base_address in SFAR register for case when "mem->spi->chip_select == 1"
> > 	qspi_writel(q, q->memmap_phy + 0x4000000, base + QUADSPI_SFAR);  
> 
> I don't want to expose the full device in the direct mapping yet (that's part of the direct-mapping API I posted here [1]). What this version of the driver does is, map only 2 time the ahb_size so that we can bypass the internal cache of the QSPI engine.
> 
> To perform any operation on second flash, we need to provide it's base address should be saved in SFAR register for this particular operation.

That's what we tried to do, we tried to make all CS start at 0 when they
are used and declare unused CS at having a size of 0.

So, say you're trying to access CS1, you should have the following
ranges:

CS0: 0 -> 0 (size = 0)
CS1: 0 -> 2 * ->ahb_buf_size (size = 2 * ->ahb_buf_size)
CS2: 2 * ->ahb_buf_size -> 2 * ->ahb_buf_size (size = 0)
CS3: 2 * ->ahb_buf_size -> 2 * ->ahb_buf_size (size = 0)

now, if you're trying to access CS3:

CS0: 0 -> 0 (size = 0)
CS1: 0 -> 0 (size = 0)
CS2: 0 -> 0 (size = 0)
CS3: 0 -> 2 * ->ahb_buf_size (size = 2 * ->ahb_buf_size)

maybe this approach does not work, but that's not clearly stated as
'not supported' in the datasheet.

> Exposing only 2 time of ahb_size is design decision but value in SFAR register should be correct.
> 
> > 
> > Thus, there should be mechanism or the entry in structure where we can have the information of the size of the connected slave device.  
> 
> Because that's exactly the kind of thing I'd like to avoid. What if the device is bigger than the reserved memory region? What if the sum of all devices does not fit in there? Here I tried to support all cases by just mapping the portion of memory we need.
> 
> So IMO, there should be mechanism to have value of start address of each slave device. This might can be done from DTS entry of each slave device connected to the controller.

Let's not put that in the DT. If we really can't re-use 0 as the start
address and make some ranges 0 in size, then let's reserve 2 *
->ahb_buf_size per chip, and be done with it.

This should leave us enough space in the AHB mem range to then support
temporary direct mappings through the direct mapping API.

Regards,

Boris

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