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Message-ID: <201806201509.fCwr8GHh%fengguang.wu@intel.com>
Date:   Wed, 20 Jun 2018 16:07:09 +0800
From:   kbuild test robot <lkp@...el.com>
To:     Ravi Bangoria <ravi.bangoria@...ux.ibm.com>
Cc:     kbuild-all@...org, oleg@...hat.com, srikar@...ux.vnet.ibm.com,
        rostedt@...dmis.org, mhiramat@...nel.org, peterz@...radead.org,
        mingo@...hat.com, acme@...nel.org,
        alexander.shishkin@...ux.intel.com, jolsa@...hat.com,
        namhyung@...nel.org, linux-kernel@...r.kernel.org, corbet@....net,
        linux-doc@...r.kernel.org, ananth@...ux.vnet.ibm.com,
        alexis.berlemont@...il.com, naveen.n.rao@...ux.vnet.ibm.com,
        Ravi Bangoria <ravi.bangoria@...ux.ibm.com>
Subject: Re: [PATCH v4 2/9] Uprobe: Change set_swbp definition

Hi Ravi,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on tip/perf/core]
[also build test WARNING on v4.18-rc1 next-20180619]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Ravi-Bangoria/Uprobes-Support-SDT-markers-having-reference-count-semaphore/20180620-120240
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm 

All warnings (new ones prefixed by >>):

   In file included from include/linux/swab.h:5:0,
                    from include/uapi/linux/byteorder/big_endian.h:13,
                    from include/linux/byteorder/big_endian.h:5,
                    from arch/arm/include/uapi/asm/byteorder.h:20,
                    from include/asm-generic/bitops/le.h:6,
                    from arch/arm/include/asm/bitops.h:342,
                    from include/linux/bitops.h:38,
                    from include/linux/kernel.h:11,
                    from arch/arm/probes/uprobes/core.c:9:
   arch/arm/probes/uprobes/core.c: In function 'set_swbp':
   arch/arm/probes/uprobes/core.c:36:32: error: dereferencing pointer to incomplete type 'struct uprobe'
         __opcode_to_mem_arm(uprobe->arch.bpinsn));
                                   ^
   include/uapi/linux/swab.h:114:54: note: in definition of macro '__swab32'
    #define __swab32(x) (__u32)__builtin_bswap32((__u32)(x))
                                                         ^
>> arch/arm/include/asm/opcodes.h:103:32: note: in expansion of macro '___opcode_swab32'
    #define __opcode_to_mem_arm(x) ___opcode_swab32(x)
                                   ^~~~~~~~~~~~~~~~
   arch/arm/probes/uprobes/core.c:36:6: note: in expansion of macro '__opcode_to_mem_arm'
         __opcode_to_mem_arm(uprobe->arch.bpinsn));
         ^~~~~~~~~~~~~~~~~~~
   arch/arm/probes/uprobes/core.c:37:1: warning: control reaches end of non-void function [-Wreturn-type]
    }
    ^

vim +/___opcode_swab32 +103 arch/arm/include/asm/opcodes.h

57b9da32 Dave Martin 2012-09-03  102  
0ce3de23 Dave Martin 2012-09-03 @103  #define __opcode_to_mem_arm(x) ___opcode_swab32(x)
0ce3de23 Dave Martin 2012-09-03  104  #define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
0ce3de23 Dave Martin 2012-09-03  105  #define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
0ce3de23 Dave Martin 2012-09-03  106  #define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
0ce3de23 Dave Martin 2012-09-03  107  #define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
0ce3de23 Dave Martin 2012-09-03  108  #define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
57b9da32 Dave Martin 2012-09-03  109  

:::::: The code at line 103 was first introduced by commit
:::::: 0ce3de23f2a520a6ac8c2179fb8f88342c4992ef ARM: 7509/1: opcodes: Make opcode byteswapping macros assembly-compatible

:::::: TO: Dave Martin <dave.martin@...aro.org>
:::::: CC: Russell King <rmk+kernel@....linux.org.uk>

---
0-DAY kernel test infrastructure                Open Source Technology Center
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