[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <187ad4e2-d72b-2267-df40-dfb178ab0e47@linux.intel.com>
Date: Fri, 22 Jun 2018 10:05:17 -0700
From: Dave Hansen <dave.hansen@...ux.intel.com>
To: Rik van Riel <riel@...riel.com>, linux-kernel@...r.kernel.org
Cc: 86@...r.kernel.org, luto@...nel.org, mingo@...nel.org,
tglx@...utronix.de, efault@....de, songliubraving@...com,
kernel-team@...com
Subject: Re: [PATCH 4/7] x86,tlb: make lazy TLB mode lazier
On 06/20/2018 12:56 PM, Rik van Riel wrote:
> This patch deals with that issue by introducing a third TLB state,
> TLBSTATE_FLUSH, which causes %CR3 to be reloaded at the next context
> switch.
With PCIDs, do we need to be a bit more explicit about what kind of %CR3
reload we have? Because, with PCIDs, we do have non-TLB-flushing %CR3
writes.
Powered by blists - more mailing lists