lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20180627094013.e42crqqufo2jqra6@paasikivi.fi.intel.com>
Date:   Wed, 27 Jun 2018 12:40:13 +0300
From:   Sakari Ailus <sakari.ailus@...ux.intel.com>
To:     Bartosz Golaszewski <brgl@...ev.pl>
Cc:     alanx.chiang@...el.com, linux-i2c <linux-i2c@...r.kernel.org>,
        andy.yeh@...el.com,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        andriy.shevchenko@...el.com,
        Rajmohan Mani <rajmohan.mani@...el.com>,
        Andy Shevchenko <andy.shevchenko@...il.com>,
        tfiga@...omium.org, jcliang@...omium.org,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Arnd Bergmann <arnd@...db.de>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>
Subject: Re: [PATCH v3 1/2] dt-bindings: at24: Add address-width property

On Wed, Jun 27, 2018 at 10:19:38AM +0200, Bartosz Golaszewski wrote:
> 2018-06-27 7:46 GMT+02:00  <alanx.chiang@...el.com>:
> > From: Alan Chiang <alanx.chiang@...el.com>
> >
> > The AT24 series chips use 8-bit address by default. If some
> > chips would like to support more than 8 bits, the at24 driver
> > should be added the compatible field for specfic chips.
> >
> > Provide a flexible way to determine the addressing bits through
> > address-width in this patch.
> >
> > Signed-off-by: Alan Chiang <alanx.chiang@...el.com>
> > Signed-off-by: Andy Yeh <andy.yeh@...el.com>
> >
> > ---
> > since v1:
> > -- Remove the address-width field in the example.
> > since v2:
> > -- Remove redundant space.
> >
> > ---
> >  Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
> > index 61d833a..aededdb 100644
> > --- a/Documentation/devicetree/bindings/eeprom/at24.txt
> > +++ b/Documentation/devicetree/bindings/eeprom/at24.txt
> > @@ -72,6 +72,8 @@ Optional properties:
> >
> >    - wp-gpios: GPIO to which the write-protect pin of the chip is connected.
> >
> > +  - address-width: number of address bits (one of 8, 16).
> > +
> >  Example:
> >
> >  eeprom@52 {
> > --
> > 2.7.4
> >
> 
> Rob,
> 
> we only have two possibilities here and the default is 8 bits.
> 
> What do you think about introducing a boolean property here called:
> 'address-width-16' instead of an integer?

I'd have thought the same, but it turns out address-width is already being
used by the at25 bindings:

Documentation/devicetree/bindings/eeprom/at25.txt

-- 
Sakari Ailus
sakari.ailus@...ux.intel.com

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ