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Message-Id: <1530173842-56851-2-git-send-email-michel.pollet@bp.renesas.com>
Date: Thu, 28 Jun 2018 09:17:12 +0100
From: Michel Pollet <michel.pollet@...renesas.com>
To: linux-renesas-soc@...r.kernel.org,
Simon Horman <horms@...ge.net.au>
Cc: phil.edworthy@...esas.com,
Michel Pollet <buserror+upstream@...il.com>,
Michel Pollet <michel.pollet@...renesas.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Magnus Damm <magnus.damm@...il.com>,
Chen-Yu Tsai <wens@...e.org>,
Kevin Hilman <khilman@...libre.com>,
Maxime Ripard <maxime.ripard@...tlin.com>,
Florian Fainelli <f.fainelli@...il.com>,
Rajendra Nayak <rnayak@...eaurora.org>,
Carlo Caione <carlo@...lessm.com>,
Stefan Wahren <stefan.wahren@...e.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v7 1/3] dt-bindings: cpu: Add Renesas R9A06G032 SMP enable method.
Add a special enable method for second CA7 of the R9A06G032
Signed-off-by: Michel Pollet <michel.pollet@...renesas.com>
Reviewed-by: Rob Herring <robh@...nel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Reviewed-by: Simon Horman <horms+renesas@...ge.net.au>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 29e1dc5..b395d107 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -219,6 +219,7 @@ described below.
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"renesas,apmu"
+ "renesas,r9a06g032-smp"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
--
2.7.4
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