linux-kernel - Re: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs

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Date:   Tue, 03 Jul 2018 10:09:33 +0200
From:   Jerome Brunet <jbrunet@...libre.com>
To:     Yixun Lan <yixun.lan@...ogic.com>,
        Boris Brezillon <boris.brezillon@...tlin.com>
Cc:     Neil Armstrong <narmstrong@...libre.com>,
        Kevin Hilman <khilman@...libre.com>,
        Carlo Caione <carlo@...one.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Miquel Raynal <miquel.raynal@...tlin.com>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Liang Yang <liang.yang@...ogic.com>,
        Qiufang Dai <qiufang.dai@...ogic.com>,
        Jian Hu <jian.hu@...ogic.com>, linux-clk@...r.kernel.org,
        linux-amlogic@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs

On Tue, 2018-07-03 at 15:36 +0800, Yixun Lan wrote:
> Hi Broris
> 
>  thanks for your quick response, and see my comments below
> 
> On 07/03/18 15:21, Boris Brezillon wrote:
> > On Tue, 3 Jul 2018 14:57:15 +0000
> > Yixun Lan <yixun.lan@...ogic.com> wrote:
> > 
> > > Add two clock bindings IDs which provided by the EMMC clock controller,
> > > These two clocks will be used by EMMC or NAND driver.
> > > 
> > > Signed-off-by: Yixun Lan <yixun.lan@...ogic.com>
> > > ---
> > >  include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
> > >  1 file changed, 14 insertions(+)
> > >  create mode 100644 include/dt-bindings/clock/emmc-clkc.h
> > > 
> > > diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
> > > new file mode 100644
> > > index 000000000000..d9972c400e58
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/emmc-clkc.h
> > > @@ -0,0 +1,14 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > > +/*
> > > + * Meson EMMC sub clock tree IDs
> > > + *
> > > + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> > > + */
> > > +
> > > +#ifndef __EMMC_CLKC_H
> > > +#define __EMMC_CLKC_H
> > > +
> > > +#define CLKID_EMMC_C_MUX				0
> > 
> > Looks like the MUX clk is the parent of the DIV one, and I guess the clk
> > driver is able to select the best parent+div pair for a requested rate.
> > Do you really need to expose the MUX to users?
> > 
> 
> Yes, It's true, the mux is parent of the div clock.
> 
> while testing for the NAND driver, I find it's kind of loose about the
> parent of the clock, so selecting the div (and let CCF decide freely) is
> actually works fine
> 
> but for the EMMC driver, especially when running at high clock, it's
> kind of picky about the parent of the clock, 

It would be nice to get an explanation about this behavior.
it seems that even of the rate provided by CLKID_SD_EMMC_X_CLK0 (main clock
controller) is correct, the eMMC cannot reliably tune with it.

Could you elaborate on this ?

> so the driver may want to
> manually choose the parent of the mux clock (example fclk_div2 here).
> That's why I'm exporting this clock ID.

ATM the EMMC driver will not use this provider. If this is the only reason, it
could be done later.

Is the NAND driver "picky" as well ?

> 
> 
> > > +#define CLKID_EMMC_C_DIV				1
> > > +
> > > +#endif
> > 
> > .
> > 
> 
> --
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