linux-kernel - [PATCH v2] usb: dwc3: of-simple: reset host controller at suspend/resume

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Message-Id: <20180716102547.10092-1-enric.balletbo@collabora.com>
Date:   Mon, 16 Jul 2018 12:25:47 +0200
From:   Enric Balletbo i Serra <enric.balletbo@...labora.com>
To:     linux-kernel@...r.kernel.org
Cc:     briannorris@...omium.org, kernel@...labora.com, heiko@...ech.de,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        linux-usb@...r.kernel.org, Felipe Balbi <balbi@...nel.org>
Subject: [PATCH v2] usb: dwc3: of-simple: reset host controller at suspend/resume

If we power off the SoC logic rail in S3, we can find that the Type-C
PHY can't initialize correctly after system resume. We need to toggle
the USB3-OTG reset before trying to initialize the PHY, or else it
times out.

    phy phy-ff800000.phy.9: phy poweron failed --> -110
    dwc3 fe900000.dwc3: failed to initialize core
    dwc3: probe of fe900000.dwc3 failed with error -110

Note that the RK3399 TRM suggests that we should keep the whole usb3
controller in reset for the duration of the Type-C PHY initialization.
However, it's hard to assert the reset in the current framework of
reset. We're still skeptical about that, and we haven't yet found a
case where this seems to have mattered. This approach is much easier, it
simply holds the USB3-OTG reset while device is supended.

The dwc3 core is going to reinitialize the controller at suspend/resume
anyway (including a "soft reset"), so it should be safe to do this.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
---
Dear all,

Now that the usb3-phy otg port support for rk3399 has been merged [1] we
found that suspend/resume is broken. The problem is well known for
ChromeOS kernels, they solved it in a similar way adding a reset pulse on
resume in the specific usb glue layer (dwc3-rockchip). In mainline,
though, we use the dwc3-of-simple glue layer instead of a specific layer
for rockchip. The patch is based on the Brian Norris work but slightly
different, it holds the reset while device is suspended. It was tested
on a Samsung Chromebook Plus with usbc docking station attached by doing
different suspend/resume cycles and checking no usb devices has been
lost.

I am not sure this is the better way to solve this but I did not find
any other way, and, as I am not sure this can be generic, the reset is only
done on rockchip platforms.

Best regards,
 Enric

[1] bfdca1736ea76345071bbc5607d18928e54909ac ('arm64: dts: rockchip: add
    usb3-phy otg-port support for rk3399')

Changes in v2:
- Use a single of_device_is_compatible() call during probe to set a driver
  flag.

 drivers/usb/dwc3/dwc3-of-simple.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index dbeff5e6ad14..40bf9e0bbc59 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -28,6 +28,7 @@ struct dwc3_of_simple {
 	int			num_clocks;
 	struct reset_control	*resets;
 	bool			pulse_resets;
+	bool			need_reset;
 };

 static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count)
@@ -93,6 +94,13 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, simple);
 	simple->dev = dev;

+	/*
+	 * Some controllers need to toggle the usb3-otg reset before trying to
+	 * initialize the PHY, otherwise the PHY times out.
+	 */
+	if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
+		simple->need_reset = true;
+
 	if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") ||
 	    of_device_is_compatible(np, "amlogic,meson-gxl-dwc3")) {
 		shared_resets = true;
@@ -201,9 +209,30 @@ static int dwc3_of_simple_runtime_resume(struct device *dev)

 	return 0;
 }
+
+static int dwc3_of_simple_suspend(struct device *dev)
+{
+	struct dwc3_of_simple *simple = dev_get_drvdata(dev);
+
+	if (simple->need_reset)
+		reset_control_assert(simple->resets);
+
+	return 0;
+}
+
+static int dwc3_of_simple_resume(struct device *dev)
+{
+	struct dwc3_of_simple *simple = dev_get_drvdata(dev);
+
+	if (simple->need_reset)
+		reset_control_deassert(simple->resets);
+
+	return 0;
+}
 #endif

 static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(dwc3_of_simple_suspend, dwc3_of_simple_resume)
 	SET_RUNTIME_PM_OPS(dwc3_of_simple_runtime_suspend,
 			dwc3_of_simple_runtime_resume, NULL)
 };
-- 
2.18.0