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Message-ID: <6dadc5a6-7bc1-0e37-4df6-0278d9046c96@xilinx.com>
Date: Thu, 19 Jul 2018 12:30:30 +0200
From: Michal Simek <michal.simek@...inx.com>
To: Jolly Shah <jolly.shah@...inx.com>, <ard.biesheuvel@...aro.org>,
<mingo@...nel.org>, <gregkh@...uxfoundation.org>,
<matt@...eblueprint.co.uk>, <sudeep.holla@....com>,
<hkallweit1@...il.com>, <keescook@...omium.org>,
<dmitry.torokhov@...il.com>, <mturquette@...libre.com>,
<sboyd@...eaurora.org>, <michal.simek@...inx.com>,
<robh+dt@...nel.org>, <mark.rutland@....com>,
<linux-clk@...r.kernel.org>
CC: <rajanv@...inx.com>, <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
Tejas Patel <tejasp@...inx.com>,
Shubhrajyoti Datta <shubhrajyoti.datta@...inx.com>,
Jolly Shah <jollys@...inx.com>
Subject: Re: [PATCH v10 10/10] drivers: clk: Add ZynqMP clock driver
Hi Stephen and Mike,
On 17.7.2018 21:59, Jolly Shah wrote:
> From: Jolly Shah <jolly.shah@...inx.com>
>
> This patch adds CCF compliant clock driver for ZynqMP.
> Clock driver queries supported clock information from
> firmware and regiters pll and output clocks with CCF.
>
> Signed-off-by: Rajan Vaja <rajanv@...inx.com>
> Signed-off-by: Tejas Patel <tejasp@...inx.com>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@...inx.com>
> Signed-off-by: Jolly Shah <jollys@...inx.com>
> ---
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile | 1 +
> drivers/clk/zynqmp/Kconfig | 10 +
> drivers/clk/zynqmp/Makefile | 4 +
> drivers/clk/zynqmp/clk-gate-zynqmp.c | 144 +++++++
> drivers/clk/zynqmp/clk-mux-zynqmp.c | 141 +++++++
> drivers/clk/zynqmp/clk-zynqmp.h | 68 ++++
> drivers/clk/zynqmp/clkc.c | 719 +++++++++++++++++++++++++++++++++++
> drivers/clk/zynqmp/divider.c | 217 +++++++++++
> drivers/clk/zynqmp/pll.c | 335 ++++++++++++++++
> include/linux/firmware/xlnx-zynqmp.h | 1 +
> 11 files changed, 1641 insertions(+)
> create mode 100644 drivers/clk/zynqmp/Kconfig
> create mode 100644 drivers/clk/zynqmp/Makefile
> create mode 100644 drivers/clk/zynqmp/clk-gate-zynqmp.c
> create mode 100644 drivers/clk/zynqmp/clk-mux-zynqmp.c
> create mode 100644 drivers/clk/zynqmp/clk-zynqmp.h
> create mode 100644 drivers/clk/zynqmp/clkc.c
> create mode 100644 drivers/clk/zynqmp/divider.c
> create mode 100644 drivers/clk/zynqmp/pll.c
DT binding was reviewed by Stephen but I can't see any review for the
driver itself. Should I wait for your review or do you want to take
binding doc 09/10 and 10/10 separately or this can go via arm-soc tree?
Thanks,
Michal
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