[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20180724072637.smhlrx4kpyh6hvwa@ninjato>
Date: Tue, 24 Jul 2018 09:26:37 +0200
From: Wolfram Sang <wsa@...-dreams.de>
To: Phil Reid <preid@...ctromag.com.au>
Cc: Wolfram Sang <wsa+renesas@...g-engineering.com>,
linux-i2c@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
kernel@...gutronix.de,
Jarkko Nikula <jarkko.nikula@...ux.intel.com>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
Mika Westerberg <mika.westerberg@...ux.intel.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH/RFT 1/6] i2c: designware: use open drain for recovery GPIO
Hi Phil,
> > So, it is not possible to read SCL status then? Hmm, currently a working
> > get_scl is required...
...
> > Well, I don't know much about this IP core and how/where it is used. I
> > just wonder what happens if another user comes along using an
> > open-drain GPIO. Is that possible?
> >
> > I assume it is the same with SDA? Non open-drain? Output only?
> >
>
> Just had a closer look at how it's setup here.
> Maybe the following helps.
Thanks for the detailed explanation. I am just afraid it is a litle too
detailed for me. I am not sure if I can read it correctly:
When you read the SCL/SDA GPIO, does it return the true state of the
SCL/SDA line or does it just reflect the value it was set to output?
> There's no concept of HiZ internally in the FPGA.
Which probably means SDA is to be treated the same as SCL -> push/pull.
> If there was some kinda of OpenDrain gpio driver that modelled a FET
> driven by a push pull GPIO I guess it could be made to work.
Still, that sounds quite unlikely to me, so we can for now assume that
all designware users will have push/pull?
Disclaimer: I have zero experience with this core, I don't know how hard
it is to modify or which versions are out there.
Thanks for your help,
Wolfram
Download attachment "signature.asc" of type "application/pgp-signature" (834 bytes)
Powered by blists - more mailing lists