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Message-Id: <96C87F41-C36B-4689-A92C-6A00D86538FA@goldelico.com>
Date: Wed, 25 Jul 2018 10:29:15 +0200
From: "H. Nikolaus Schaller" <hns@...delico.com>
To: Ladislav Michl <ladis@...ux-mips.org>
Cc: Marek Belisko <marek@...delico.com>,
Benoît Cousson <bcousson@...libre.com>,
Tony Lindgren <tony@...mide.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
linux-omap@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, letux-kernel@...nphoenux.org
Subject: Re: [PATCH 32/32] ARM: dts: omap3-gta04a5one: define GTA04A5 variant with OneNAND
> Am 25.07.2018 um 10:20 schrieb Ladislav Michl <ladis@...ux-mips.org>:
>
> On Wed, Jul 25, 2018 at 08:59:04AM +0200, H. Nikolaus Schaller wrote:
>> GTA04A5 has been produced with MCP chips either with
>> 512MB RAM + 512MB NAND
>> 512MB RAM + 1024MB NAND
>> 1024MB RAM + 512MB OneNAND
>>
>> RAM setup is done by U-Boot (MLO/SPL) but OneNAND needs
>> a different setup of the GPMC. So we need to derive a
>> DTB variant that modifies the gpmc and nand setup.
>
> Just a suggestion... This way your user needs to know which variant is dealing
> with. It is similar situation as with IGEPv2 with cames with various setup
> either with NAND or OneNAND. Both NAND and OneNAND nodes are present in DTB
> and enabled by U-Boot approriately. So single U-Boot binary and DTB is enough
> to deal with all variants.
Well, the standard U-Boot used on this type of devices just loads this or that
.dtb. It does not modify it or enable/disable nodes. So we'd prefer to have it
this way.
>
> ladis
>
>> Signed-off-by: H. Nikolaus Schaller <hns@...delico.com>
>> ---
>> arch/arm/boot/dts/omap3-gta04a5one.dts | 114 +++++++++++++++++++++++++++++++++
>> 1 file changed, 114 insertions(+)
>> create mode 100644 arch/arm/boot/dts/omap3-gta04a5one.dts
>>
>> diff --git a/arch/arm/boot/dts/omap3-gta04a5one.dts b/arch/arm/boot/dts/omap3-gta04a5one.dts
>> new file mode 100644
>> index 000000000000..9b7bbdc344b3
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap3-gta04a5one.dts
>> @@ -0,0 +1,114 @@
>> +/*
>> + * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@...delico.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include "omap3-gta04a5.dts"
>> +
>> +&omap3_pmx_core {
>> + model = "Goldelico GTA04A5/Letux 2804 with OneNAND";
>> +
>> + gpmc_pins: pinmux_gpmc_pins {
>> + pinctrl-single,pins = <
>> +
>> + /* address lines */
>> + OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
>> + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
>> + OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
>> +
>> + /* data lines, gpmc_d0..d7 not muxable according to TRM */
>> + OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
>> + OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
>> + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
>> + OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
>> + OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
>> + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
>> + OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
>> + OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
>> +
>> + /*
>> + * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
>> + * according to TRM. OneNAND seems to require PIN_INPUT on clock.
>> + */
>> + OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
>> + OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
>> + >;
>> + };
>> +};
>> +
>> +&gpmc {
>> + /* switch inherited setup to OneNAND */
>> +
>> + ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gpmc_pins>;
>> +
>> + /delete-node/ nand@0,0;
>> +
>> + onenand@0,0 {
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "ti,omap2-onenand";
>> + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
>> +
>> + gpmc,sync-read;
>> + gpmc,sync-write;
>> + gpmc,burst-length = <16>;
>> + gpmc,burst-read;
>> + gpmc,burst-wrap;
>> + gpmc,burst-write;
>> + gpmc,device-width = <2>;
>> + gpmc,mux-add-data = <2>;
>> + gpmc,cs-on-ns = <0>;
>> + gpmc,cs-rd-off-ns = <87>;
>> + gpmc,cs-wr-off-ns = <87>;
>> + gpmc,adv-on-ns = <0>;
>> + gpmc,adv-rd-off-ns = <10>;
>> + gpmc,adv-wr-off-ns = <10>;
>> + gpmc,oe-on-ns = <15>;
>> + gpmc,oe-off-ns = <87>;
>> + gpmc,we-on-ns = <0>;
>> + gpmc,we-off-ns = <87>;
>> + gpmc,rd-cycle-ns = <112>;
>> + gpmc,wr-cycle-ns = <112>;
>> + gpmc,access-ns = <81>;
>> + gpmc,page-burst-access-ns = <15>;
>> + gpmc,bus-turnaround-ns = <0>;
>> + gpmc,cycle2cycle-delay-ns = <0>;
>> + gpmc,wait-monitoring-ns = <0>;
>> + gpmc,clk-activation-ns = <5>;
>> + gpmc,wr-data-mux-bus-ns = <30>;
>> + gpmc,wr-access-ns = <81>;
>> + gpmc,sync-clk-ps = <15000>;
>> +
>> + x-loader@0 {
>> + label = "X-Loader";
>> + reg = <0 0x80000>;
>> + };
>> +
>> + bootloaders@...00 {
>> + label = "U-Boot";
>> + reg = <0x80000 0x1c0000>;
>> + };
>> +
>> + bootloaders_env@...000 {
>> + label = "U-Boot Env";
>> + reg = <0x240000 0x40000>;
>> + };
>> +
>> + kernel@...000 {
>> + label = "Kernel";
>> + reg = <0x280000 0x600000>;
>> + };
>> +
>> + filesystem@...000 {
>> + label = "File System";
>> + reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */
>> + };
>> +
>> + };
>> +};
>> --
>> 2.12.2
>>
>> --
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