linux-kernel - Re: [RFC V4 0/3] arm_pmu: acpi: variant support and QCOM Falkor extensions

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20180725151641.GC6866@arm.com>
Date:   Wed, 25 Jul 2018 16:16:41 +0100
From:   Will Deacon <will.deacon@....com>
To:     J. Agustín Vega-Frías 
        <agustin.vega.frias@...il.com>
Cc:     Agustin Vega-Frias <agustinv@...eaurora.org>,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-acpi@...r.kernel.org, Mark Rutland <mark.rutland@....com>,
        Jeremy Linton <jeremy.linton@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Marc Zyngier <marc.zyngier@....com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Phani Pabba <pabba@...eaurora.org>,
        Richard Ruigrok <rruigrok@...eaurora.org>,
        Vijaya Kilari <vkilari@...eaurora.org>,
        Jeff Hugo <jhugo@...eaurora.org>,
        Rahul Ramasubramanian <rahulr@...eaurora.org>
Subject: Re: [RFC V4 0/3] arm_pmu: acpi: variant support and QCOM Falkor
 extensions

On Sun, Jul 15, 2018 at 03:35:45PM -0500, J. Agustín Vega-Frías wrote:
> On Fri, Jul 13, 2018 at 10:33 AM, Will Deacon <will.deacon@....com> wrote:
> > I'm mostly ok with this approach, but I have a concern with the way in which
> > the sysfs interface for carving up the config fields is implemented. If this
> > is intended to be a strict extension to the armv8 pmu architecture, then I
> > don't think you should be overriding the attr_groups entirely. Rather, you
> > should be taking the attr_groups from pmuv3 and then extending them in a way
> > which avoids overlapping field allocations by construction.
> >
> > As it stands, you already have an overlap between the pcc bit and the
> > chained counter bit which Suzuki has implemented and it will be very easy to
> > introduce API breakage if we don't enforce this as part of the design.
> >
> > Will
> 
> FYI, I left Qualcomm on July 6, one of my former colleagues will submit
> new iterations of this series. I will continue to comment on this and future
> patchsets as a courtesy to my former colleagues and the community.
> 
> Thanks for pointing out the sysfs issue. My suggestion on how to address it is:
> 
> 1. Reserve config and config1 for architectural format attributes and
>    config2 for extension format attributes.
> 2. Add a struct attribute ** parameter to the extension init function so
>    extensions can return the new attributes.
> 3. The extension framework code in arm_pmu_acpi.c can then allocate a new
>    attribute array to contain the base and extension attributes and ensure
>    all the new attributes are on config2.
> 
> Though a more elaborate approach can be implemented to find conflicts in
> bit usage within config fields, it would require much more code for a
> relatively simple problem. Thoughts?

As long as you're happy to live inside config2, that sounds sensible to me.

Will