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Message-ID: <CAN8YU5Pwn-dqU=QwiG=Wmg2QbEj2Z5U-uEQZcc3huZw-w568jA@mail.gmail.com>
Date: Thu, 9 Aug 2018 08:36:00 +0200
From: Andrea Merello <andrea.merello@...il.com>
To: Rob Herring <robh@...nel.org>
Cc: Vinod <vkoul@...nel.org>, dan.j.williams@...el.com,
michal.simek@...inx.com, appana.durga.rao@...inx.com,
dmaengine@...r.kernel.org,
v4-000linux-arm-kernel@...ts.infradead.org,
linux-kernel <linux-kernel@...r.kernel.org>,
Mark Rutland <mark.rutland@....com>,
devicetree <devicetree@...r.kernel.org>,
Radhey Shyam Pandey <radhey.shyam.pandey@...inx.com>
Subject: Re: [PATCH v4 3/7] dt-bindings: dmaengine: xilinx_dma: add optional
xlnx,sg-length-width property
On Tue, Aug 7, 2018 at 4:56 PM, Rob Herring <robh@...nel.org> wrote:
> On Thu, Aug 02, 2018 at 04:10:08PM +0200, Andrea Merello wrote:
>> The width of the "length register" cannot be autodetected, and it is now
>> specified with a DT property. Add DOC for it.
>>
>> Cc: Rob Herring <robh+dt@...nel.org>
>> Cc: Mark Rutland <mark.rutland@....com>
>> Cc: devicetree@...r.kernel.org
>> Cc: Radhey Shyam Pandey <radhey.shyam.pandey@...inx.com>
>> Signed-off-by: Andrea Merello <andrea.merello@...il.com>
>> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@...inx.com>
>> ---
>> Changes in v2:
>> - change property name
>> - property is now optional
>> - cc DT maintainer
>> Changes in v3:
>> - reword
>> - cc DT maintainerS and ML
>> Changes in v4:
>> - specify the unit, the valid range and the default value
>> ---
>> Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
>> index a2b8bfaec43c..aec4a41a03ae 100644
>> --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
>> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
>> @@ -41,6 +41,10 @@ Optional properties:
>> - xlnx,include-sg: Tells configured for Scatter-mode in
>> the hardware.
>> Optional properties for AXI DMA:
>> +- xlnx,sg-length-width: Should be set to the width in bits of the length
>> + register as configured in h/w. Takes values {8...26}. If the property
>> + is missing or invalid then the default value 23 is used. This is the
>> + maximum value that is supported by all IP versions.
>
> If 23 is the max, then why is the range 8-26?
26 In the max possible value and it is supported by some HW IP flavours.
23 is the max value supported by ALL HW IP flavours
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