linux-kernel - Re: [LINUX PATCH v10 2/2] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller

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Message-ID: <20180821093125.05fb46a4@xps13>
Date:   Tue, 21 Aug 2018 09:31:25 +0200
From:   Miquel Raynal <miquel.raynal@...tlin.com>
To:     Naga Sureshkumar Relli <nagasure@...inx.com>
Cc:     Boris Brezillon <boris.brezillon@...tlin.com>,
        "richard@....at" <richard@....at>,
        "dwmw2@...radead.org" <dwmw2@...radead.org>,
        "computersforpeace@...il.com" <computersforpeace@...il.com>,
        "marek.vasut@...il.com" <marek.vasut@...il.com>,
        "kyungmin.park@...sung.com" <kyungmin.park@...sung.com>,
        "absahu@...eaurora.org" <absahu@...eaurora.org>,
        "peterpandong@...ron.com" <peterpandong@...ron.com>,
        "frieder.schrempf@...eet.de" <frieder.schrempf@...eet.de>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Michal Simek <michals@...inx.com>,
        "nagasureshkumarrelli@...il.com" <nagasureshkumarrelli@...il.com>
Subject: Re: [LINUX PATCH v10 2/2] mtd: rawnand: arasan: Add support for
 Arasan NAND Flash Controller

Hi Naga,

> > And why is it an s32 and not a u32?  
> To monitor NAND_CMD_STATUS.
> Sometimes core will just send status command without reading back the status data and later
> It will try to read one byte using ->exec_op().
> So Arasan has FLASH_STS register and whenever we initiate a status command, the controller
> Will update this register with the value returned by the flash device.
> So we need to return this value when core is asking about 1 byte status value without issuing the command.
> And in driver we are using memset(nfc_op, 0, sizeof(struct anfc_op)), this will make cmnds[4] to zeros but 0x0 is also
> NAND_CMD_READ0, so inorder to differentiate whether to give status data or not, I just assigned 
> 	nfc_op->cmnds[0] = NAND_CMD_NONE;
> 
> May be this case we can now eliminate as per your suggestion(defining a separate hook for each pattern) and thanks for that.
> >   
> > > +	u32 type;
> > > +	u32 len;
> > > +	u32 naddrs;
> > > +	u32 col;
> > > +	u32 row;
> > > +	unsigned int data_instr_idx;
> > > +	unsigned int rdy_timeout_ms;
> > > +	unsigned int rdy_delay_ns;
> > > +	const struct nand_op_instr *data_instr; };  
> > 
> > Please make sure you actually need to redefine all these fields. Looks like some them could be
> > extracted directly from the nand_op_instr objects.  
> Ok, all these values are getting updated in anfc_parse_instructions()

In anfc_parse_instructions():

+			nfc_op->data_instr = instr;
+			nfc_op->type = NAND_OP_DATA_IN_INSTR;

This looks pointless.

+			nfc_op->data_instr_idx = op_id;
+			break;
+		case NAND_OP_DATA_OUT_INSTR:
+			nfc_op->data_instr = instr;
+			nfc_op->type = NAND_OP_DATA_IN_INSTR;
+			nfc_op->data_instr_idx = op_id;
+			break;
+		case NAND_OP_WAITRDY_INSTR:
+			nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;

This one also.

+			nfc_op->rdy_delay_ns = instr->delay_ns;

And this one too.

Once you'll have a per pattern callback, I suppose you won't need it
anymore.

> >   
> > > +
> > > +/**
> > > + * struct anfc_nand_chip - Defines the nand chip related information
> > > + * @node:		used to store NAND chips into a list.
> > > + * @chip:		NAND chip information structure.
> > > + * @bch:		Bch / Hamming mode enable/disable.
> > > + * @bchmode:		Bch mode.  
> > 
> > What's the difference between bch and bchmode?  
> @bch -> to select error correction method(either BCH or Hamming)
> @bchmode -> to select ECC correctability (4/8/12/24 bit ECC)

Then something like "strength" or "ecc_strength" would be more
meaningful.


Thanks,
Miquèl