linux-kernel - Re: [andriy.shevchenko@...ux.intel.com: Re: [PATCH] spi: dw-mmio: add MSCC Jaguar2 support]

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Date:   Wed, 29 Aug 2018 19:52:54 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Mark Brown <broonie@...nel.org>
Cc:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        linux-spi <linux-spi@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        allan.nielsen@...rochip.com,
        Alexandre Belloni <alexandre.belloni@...tlin.com>
Subject: Re: [andriy.shevchenko@...ux.intel.com: Re: [PATCH] spi: dw-mmio: add
 MSCC Jaguar2 support]

On Wed, Aug 29, 2018 at 6:16 PM Mark Brown <broonie@...nel.org> wrote:
>
> On Wed, Aug 29, 2018 at 06:09:55PM +0300, Andy Shevchenko wrote:
> > ----- Forwarded message from Andy Shevchenko <andriy.shevchenko@...ux.intel.com> -----
> >
> > Date: Wed, 29 Aug 2018 18:08:31 +0300
> > From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> > To: Alexandre Belloni <alexandre.belloni@...tlin.com>
> > Subject: Re: [PATCH] spi: dw-mmio: add MSCC Jaguar2 support
> > User-Agent: Mutt/1.10.1 (2018-07-13)
> >
> > On Wed, Aug 29, 2018 at 02:45:48PM +0200, Alexandre Belloni wrote:
> > > Unfortunately, the Jaguar2 CPU_SYSTEM_CTRL register set has a different
> > > layout than the Ocelot one. Handle that while keeping most of the code
> > > common.
> >
> > > -#define OCELOT_IF_SI_OWNER_MASK                    GENMASK(5, 4)
> >
> > > +                      0x3 << if_si_owner_offset,
> >
> > Perhaps,
> >
> > #define MSCC_IF_SI_OWNER_MASK         GENMASK(1, 0)
>
> Oops, sorry - that seems to have been eaten somewhere.  :(

Nothing to sorry about, I'm in a process on move to mutt, so, I
mispushed 'r' (Reply) instead of 'g' (Group Reply).
I just forwarded the first one.

-- 
With Best Regards,
Andy Shevchenko