linux-kernel - Re: [PATCH RESEND v1 2/5] drivers: pinctrl: msm: enable PDC interrupt only during suspend

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <153609843656.119890.7258329648640765778@swboyd.mtv.corp.google.com>
Date:   Tue, 04 Sep 2018 15:00:36 -0700
From:   Stephen Boyd <swboyd@...omium.org>
To:     Lina Iyer <ilina@...eaurora.org>
Cc:     bjorn.andersson@...aro.org, evgreen@...omium.org,
        linus.walleij@...aro.org, marc.zyngier@....com,
        rplsssn@...eaurora.org, linux-kernel@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, rnayak@...eaurora.org,
        devicetree@...r.kernel.org, andy.gross@...aro.org,
        dianders@...omium.org
Subject: Re: [PATCH RESEND v1 2/5] drivers: pinctrl: msm: enable PDC interrupt only
 during suspend

Quoting Lina Iyer (2018-09-04 14:09:34)
> On Mon, Aug 27 2018 at 14:01 -0600, Stephen Boyd wrote:
> >
> >Can't we just configure a different chained IRQ handler with
> >irq_set_chained_handler_and_data() for each of the GPIO IRQs that are
> >handled by PDC to be the interrupts provide by the PDC irq controller
> >that match the GPIOs? And then set their parent irq with
> >irq_set_parent() for completeness? And also move those GPIOs from the
> >existing msm_gpio irqchip to a different PDC gpio irqchip that does
> >nothing besides push irqchip calls up to the PDC irqchip? Then we don't
> >even have to think about resending anything and we can rely on PDC to do
> >all the interrupt sensing all the time but still provide the irqs from
> >the GPIO controller.
> >
> Seems like the irqchips need to be in hierarchy for this to work, which
> is not the case with TLMM and the PDC, currently.
> 

Why? Does something mandate that the chained irq is also the
hierarchical parent irqchip?