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Date: Wed, 5 Sep 2018 12:20:53 +0200 From: Borislav Petkov <bp@...en8.de> To: Manish Narani <manish.narani@...inx.com>, robh+dt@...nel.org Cc: mark.rutland@....com, michal.simek@...inx.com, mchehab@...nel.org, leoyang.li@....com, amit.kucheria@...aro.org, olof@...om.net, sgoud@...inx.com, anirudh@...inx.com, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-edac@...r.kernel.org Subject: Re: [PATCH v5 4/4] arm64: zynqmp: Add DDRC node On Fri, Aug 31, 2018 at 06:57:50PM +0530, Manish Narani wrote: > Add ddrc memory controller node in dts. The size mentioned in dts is > 0x30000, because we need to access DDR_QOS INTR registers located at > 0xFD090208 from this driver. > > Signed-off-by: Manish Narani <manish.narani@...inx.com> > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 29ce234..a81d3b16 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -355,6 +355,13 @@ > xlnx,bus-width = <64>; > }; > > + mc: memory-controller@...70000 { > + compatible = "xlnx,zynqmp-ddrc-2.40a"; > + reg = <0x0 0xfd070000 0x0 0x30000>; > + interrupt-parent = <&gic>; > + interrupts = <0 112 4>; > + }; > + > gem0: ethernet@...b0000 { > compatible = "cdns,zynqmp-gem", "cdns,gem"; > status = "disabled"; > -- This still needs Rob's ACK. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
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