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Message-ID: <alpine.DEB.2.21.1809101158080.1402@nanos.tec.linutronix.de>
Date:   Mon, 10 Sep 2018 12:04:00 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Jiri Kosina <jikos@...nel.org>
cc:     Ingo Molnar <mingo@...hat.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Josh Poimboeuf <jpoimboe@...hat.com>,
        Andrea Arcangeli <aarcange@...hat.com>,
        "Woodhouse, David" <dwmw@...zon.co.uk>,
        Andi Kleen <ak@...ux.intel.com>,
        Tim Chen <tim.c.chen@...ux.intel.com>,
        "Schaufler, Casey" <casey.schaufler@...el.com>,
        linux-kernel@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH v5 2/2] x86/speculation: Enable cross-hyperthread spectre
 v2 STIBP mitigation

On Mon, 10 Sep 2018, Jiri Kosina wrote:
> +static void update_stibp_msr(void *info)
> +{
> +	wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
> +}
> +
> +void arch_smt_update(void)
> +{
> +	if (stibp_needed()) {

  	if (!stib_needed())
		return;

spares you an indentation level.

> +		u64 mask;

Newline between declarations and code please.

> +		mutex_lock(&spec_ctrl_mutex);
> +		mask = x86_spec_ctrl_base;
> +		if (cpu_smt_control == CPU_SMT_ENABLED)
> +			mask |= SPEC_CTRL_STIBP;
> +		else
> +			mask &= ~SPEC_CTRL_STIBP;
> +
> +		if (mask != x86_spec_ctrl_base) {
> +			pr_info("Spectre v2 cross-process SMT mitigation: %s STIBP\n",
> +					cpu_smt_control == CPU_SMT_ENABLED ?
> +						"Enabling" : "Disabling");
> +			x86_spec_ctrl_base = mask;
> +			on_each_cpu(update_stibp_msr, NULL, 1);
> +		}
> +		mutex_unlock(&spec_ctrl_mutex);
> +	}
> +}
> +

That looks much more palatable. One missing piece is the sysfs mitigation
file for spectre v2. That should reflect STIPB state as well.

Thanks,

	tglx

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